Taiwan semiconductor manufacturing company, ltd. (20240379546). Via Structures simplified abstract

Via Structures

Organization Name

taiwan semiconductor manufacturing company, ltd.

Inventor(s)

Jhon Jhy Liaw of Hsinchu County (TW)

Via Structures - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240379546 titled 'Via Structures

The abstract describes a device with a substrate, a fin, source and drain features, a gate structure, gate via, source via, and drain via. The fin includes channel layers engaged by the gate stack, and the source and drain vias have different dimensions.

• Device includes substrate, fin, source and drain features, gate structure, gate via, source via, and drain via.
• Fin has channel layers engaged by gate stack.
• Source via and drain via have different dimensions along different directions.
• Ratio of dimensions in source via and drain via is compared.

Potential Applications: - Semiconductor industry for advanced transistors. - Electronics industry for high-performance devices.

Problems Solved: - Improved performance and efficiency of transistors. - Enhanced control over electron flow in devices.

Benefits: - Higher speed and lower power consumption in electronic devices. - Increased reliability and longevity of semiconductor components.

Commercial Applications: - Production of faster and more energy-efficient electronic devices. - Integration into various consumer electronics for improved performance.

Questions about the technology: 1. How does the device improve the efficiency of electronic components? 2. What are the potential challenges in scaling up the production of these devices?

Frequently Updated Research: - Ongoing research on optimizing the dimensions of source and drain vias for better device performance.

Original Abstract Submitted

a device includes a substrate having a top surface, a fin extending lengthwise along a first direction, a source feature and a drain feature, a gate structure having a gate stack extending along a second direction perpendicular to the first direction and interposing between the source and drain features, a gate via directly disposed on the gate stack, a source via electrically connecting the source feature, and a drain via electrically connecting the drain feature. the fin includes a stack of channel layers engaged by the gate stack. the source via has a first dimension along the second direction and a second dimension along the first direction, the drain via feature has a third dimension along the second direction and a fourth dimension along the first direction. a ratio of the first dimension to the second dimension is greater than a ratio of the third dimension to the fourth dimension.