Taiwan semiconductor manufacturing company, ltd. (20240347515). PACKAGE STRUCTURE simplified abstract
Contents
PACKAGE STRUCTURE
Organization Name
taiwan semiconductor manufacturing company, ltd.
Inventor(s)
Ming-Fa Chen of Taichung City (TW)
Sung-Feng Yeh of Taipei City (TW)
Tzuan-Horng Liu of Taoyuan City (TW)
Chao-Wen Shih of Hsinchu County (TW)
PACKAGE STRUCTURE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240347515 titled 'PACKAGE STRUCTURE
The chip structure described in the abstract consists of two semiconductor chips, with the second chip embedded within the first chip. The first chip includes a substrate, interconnection layer, protection layer, gap fill layer, and conductive vias. The second chip includes its own substrate, interconnection layer, protection layer, and conductive vias, and is bonded to the protection layer of the first chip.
- First semiconductor chip with substrate, interconnection layer, protection layer, gap fill layer, and conductive vias
- Second semiconductor chip embedded within the first chip
- Second chip includes substrate, interconnection layer, protection layer, and conductive vias
- Bonding of second chip to protection layer of first chip
- Complex chip structure for enhanced functionality
Potential Applications: - Advanced semiconductor devices - Integrated circuits - Microelectronics
Problems Solved: - Improved chip integration - Enhanced electrical connectivity - Space-saving design
Benefits: - Increased performance - Compact size - Enhanced reliability
Commercial Applications: Title: "Innovative Chip Structure for Advanced Semiconductor Devices" This technology can be utilized in the development of high-performance electronic devices, such as smartphones, tablets, and computers. The compact design and improved functionality make it ideal for various consumer electronics and industrial applications.
Questions about the technology: 1. How does the embedding of the second chip within the first chip enhance overall performance? 2. What are the specific advantages of using conductive vias in the chip structure?
Original Abstract Submitted
a chip structure includes first and second semiconductor chips. the first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer. the second semiconductor chip is embedded within the first semiconductor chip and surrounded by the gap fill layer and the first conductive vias, wherein the second semiconductor chip includes a second semiconductor substrate, a second interconnection layer located on the second semiconductor substrate, a second protection layer located on the second interconnection layer, and second conductive vias embedded in the second protection layer and electrically connected with the second interconnection layer, wherein the second semiconductor substrate is bonded to the first protection layer.
