Taiwan semiconductor manufacturing company, ltd. (20240347467). PACKAGE STRUCTURE simplified abstract

PACKAGE STRUCTURE

Organization Name

taiwan semiconductor manufacturing company, ltd.

Inventor(s)

Shih-Ting Lin of Taipei City (TW)

Chi-Hsi Wu of Hsinchu City (TW)

Chen-Hua Yu of Hsinchu City (TW)

Szu-Wei Lu of Hsinchu City (TW)

PACKAGE STRUCTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240347467 titled 'PACKAGE STRUCTURE

The patent application describes a package structure that includes multiple semiconductor dies, an insulating encapsulant, a redistribution layer, and connecting elements. The insulating encapsulant encases the semiconductor dies, while the redistribution layer is placed on top of the encapsulant in a build-up direction and is electrically connected to the semiconductor dies. The redistribution layer consists of conductive lines, conductive vias, and dielectric layers stacked alternately, with the lateral dimension of the vias increasing along the build-up direction. The connecting elements are located between the redistribution layer and the semiconductor dies, with a body portion connected to the dies and a via portion connected to the redistribution layer, where the lateral dimension of the via portion decreases along the build-up direction.

• The package structure includes multiple semiconductor dies, an insulating encapsulant, a redistribution layer, and connecting elements.
• The insulating encapsulant encases the semiconductor dies, providing protection and insulation.
• The redistribution layer is placed on top of the encapsulant in a build-up direction and is electrically connected to the semiconductor dies.
• The redistribution layer consists of conductive lines, conductive vias, and dielectric layers stacked alternately, enhancing electrical connectivity.
• The lateral dimension of the vias increases along the build-up direction, optimizing signal transmission.
• The connecting elements bridge the gap between the redistribution layer and the semiconductor dies, ensuring secure electrical connections.
• The body portion of the connecting elements is joined with the semiconductor dies, while the via portion is connected to the redistribution layer, facilitating efficient signal transfer.

Potential Applications: - This technology can be applied in the manufacturing of advanced semiconductor packages for various electronic devices. - It can be used in high-performance computing systems, telecommunications equipment, and automotive electronics.

Problems Solved: - Provides improved electrical connectivity between semiconductor dies and redistribution layers. - Enhances signal transmission efficiency within package structures. - Ensures secure and reliable connections in complex electronic systems.

Benefits: - Enhanced performance and reliability of semiconductor packages. - Increased signal transmission efficiency. - Simplified manufacturing processes for advanced electronic devices.

Commercial Applications: Title: Advanced Semiconductor Package Structure for Enhanced Connectivity This technology can be utilized in the production of high-performance electronic devices, catering to industries such as telecommunications, automotive, and computing. The improved connectivity and signal transmission efficiency offered by this package structure can lead to more reliable and efficient electronic systems.

Questions about the technology: 1. How does the lateral dimension of the vias impact signal transmission efficiency? 2. What are the potential cost-saving benefits of using this advanced package structure in electronic device manufacturing?

Original Abstract Submitted

a package structure includes a plurality of semiconductor dies, an insulating encapsulant, a redistribution layer and a plurality of connecting elements. the insulating encapsulant is encapsulating the plurality of semiconductor dies. the redistribution layer is disposed on the insulating encapsulant in a build-up direction and electrically connected to the plurality of semiconductor dies, wherein the redistribution layer includes a plurality of conductive lines, a plurality of conductive vias and a plurality of dielectric layers alternately stacked, and a lateral dimension of the plurality of conductive vias increases along the build-up direction. the connecting elements are disposed in between the redistribution layer and the semiconductor dies, wherein the connecting elements includes a body portion joined with the semiconductor dies and a via portion joined with the redistribution layer, wherein a lateral dimension of the via portion decreases along the build-up direction.