Taiwan semiconductor manufacturing company, ltd. (20240338507). Hybrid Node Chiplet Stacking Design simplified abstract

Hybrid Node Chiplet Stacking Design

Organization Name

taiwan semiconductor manufacturing company, ltd.

Inventor(s)

Jen-Yuan Chang of Hsinchu City (TW)

Jheng-Hong Jiang of Hsinchu (TW)

Chin-Chou Liu of Hsinchu County (TW)

Long Song Lin of Taipei City (TW)

Hybrid Node Chiplet Stacking Design - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240338507 titled 'Hybrid Node Chiplet Stacking Design

• • Simplified Explanation:**

This patent application discusses methods for creating multichip, hybrid node stacked package designs from single chip designs using artificial intelligence techniques.

• • Key Features and Innovation:**
• Utilizes machine learning to disassemble single chip designs into chiplets with different functions and process nodes.
• Integrates chiplets into a stacked chip package structure, enabling heterogenous integration and advanced packaging technologies.
• Enhances design for manufacturability of single chip designs.
• Aims to reduce manufacturing costs and system size provided by single chip designs.

• • Potential Applications:**

This technology could be applied in the semiconductor industry for creating more efficient and cost-effective multichip packages.

• • Problems Solved:**

Addresses the challenge of integrating different functions and process nodes in a single chip design, as well as improving manufacturability and reducing costs.

• • Benefits:**
• Facilitates heterogenous integration.
• Enhances design for manufacturability.
• Reduces manufacturing costs.
• Enables the creation of more compact systems.

• • Commercial Applications:**

Potential commercial applications include the production of advanced semiconductor packages for various electronic devices.

• • Prior Art:**

Readers can explore prior art related to multichip packaging designs and artificial intelligence techniques in the semiconductor industry.

• • Frequently Updated Research:**

Stay informed about the latest advancements in multichip packaging technologies and artificial intelligence applications in semiconductor design.

• • Questions about Multichip, Hybrid Node Stacked Package Designs:**

1. How does this technology improve the efficiency of semiconductor packaging? 2. What are the potential cost-saving benefits of using multichip, hybrid node stacked package designs in the semiconductor industry?

Original Abstract Submitted

the present disclosure is directed to methods for generating a multichip, hybrid node stacked package designs from single chip designs using artificial intelligence techniques, such as machine learning. the methods disclosed herein can facilitate heterogenous integration using advanced packaging technologies, enlarge design for manufacturability of single chip designs, and/or reduce cost to manufacture and/or size of systems provided by single chip designs. an exemplary method includes receiving a single chip design for a single chip of a single process node, wherein the single chip design has design specifications and generating a multichip, hybrid node design from the single chip design by disassembling the single chip design into chiplets having different functions and different process nodes based on the design specifications and integrating the chiplets into a stacked chip package structure.