Taiwan semiconductor manufacturing company, ltd. (20240297499). ESD PROTECTION CIRCUIT simplified abstract
Contents
ESD PROTECTION CIRCUIT
Organization Name
taiwan semiconductor manufacturing company, ltd.
Inventor(s)
Wun-Jie Lin of Hsinchu City (TW)
Kuo-Ji Chen of New Taipei City (TW)
ESD PROTECTION CIRCUIT - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240297499 titled 'ESD PROTECTION CIRCUIT
The abstract describes an ESD clamp circuit with an ESD detection circuit that outputs control signals in response to an ESD event. The discharge circuit includes a p-type transistor and an n-type transistor to establish ESD discharge paths.
- ESD clamp circuit with ESD detection circuit
- Output control signals in response to ESD event
- Discharge circuit with p-type and n-type transistors
- Establish ESD discharge paths
- Includes parasitic SCR in second discharge path
Potential Applications: - Electronic devices - Circuit protection systems - Integrated circuits
Problems Solved: - Protection against ESD events - Prevent damage to electronic components
Benefits: - Enhanced ESD protection - Improved reliability of electronic devices
Commercial Applications: Title: "ESD Clamp Circuit for Enhanced Protection in Electronic Devices" This technology can be used in various electronic devices to prevent damage from ESD events, ensuring the reliability and longevity of the devices. The market implications include increased demand for ESD protection solutions in the electronics industry.
Prior Art: Researchers can explore prior patents related to ESD protection circuits and semiconductor devices to understand the evolution of such technologies.
Frequently Updated Research: Researchers may find updated studies on ESD protection techniques and semiconductor device advancements relevant to this technology.
Questions about ESD Clamp Circuits: 1. How does the ESD detection circuit differentiate between ESD events and normal operation? 2. What are the key factors influencing the efficiency of the discharge paths in the ESD clamp circuit?
Original Abstract Submitted
an esd clamp circuit has an esd detection circuit connected between a first terminal and a second terminal, with a first output node and a second output node. the esd detection circuit is configured to output respective first and second control signals at the first and second output nodes in response to an esd event. a discharge circuit includes a p-type transistor having a source, a drain and a gate, with the gate connected to the first output node. an n-type transistor has a source, a drain and a gate, with the gate connected to the second output node. the drain is connected to the drain of the p-type transistor. the discharge circuit is configured to establish a first esd discharge path from the first terminal, through the p-type transistor and the n-type transistor, to the second terminal, and to further establish a second esd discharge path in parallel with the first esd discharge path. the second esd discharge path includes a parasitic silicon controlled rectifier (scr).
