Taiwan semiconductor manufacturing company, ltd. (20240234299). STACKED VIA STRUCTURE simplified abstract

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STACKED VIA STRUCTURE

Organization Name

taiwan semiconductor manufacturing company, ltd.

Inventor(s)

Po-Han Wang of Hsinchu City (TW)

Hung-Jui Kuo of Hsinchu City (TW)

Yu-Hsiang Hu of Hsinchu City (TW)

STACKED VIA STRUCTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240234299 titled 'STACKED VIA STRUCTURE

The patent application describes a stacked via structure consisting of multiple layers and conductive vias for electrical connections.

  • The structure includes a first dielectric layer with a via opening, a first conductive via, and a first redistribution wiring.
  • A second dielectric layer is placed on top of the first layer, along with a second conductive via and a second via opening.
  • The second conductive via is connected to the first redistribution wiring through the second via opening, creating a multi-layered electrical pathway.

Potential Applications: This technology can be used in semiconductor manufacturing, integrated circuits, and electronic devices requiring complex wiring configurations.

Problems Solved: The stacked via structure solves the problem of efficiently routing electrical connections in compact electronic devices with limited space.

Benefits: The structure allows for increased circuit density, improved signal integrity, and enhanced performance of electronic devices.

Commercial Applications: This technology can be applied in the production of smartphones, tablets, computers, and other consumer electronics to enhance their functionality and reliability.

Questions about Stacked Via Structure: 1. How does the stacked via structure improve the performance of electronic devices? 2. What are the key advantages of using a multi-layered via structure in semiconductor manufacturing?


Original Abstract Submitted

a stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. the first dielectric layer includes a first via opening. the first conductive via is in the first via opening. a first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. the first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. the second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. the second dielectric layer includes a second via opening. the second conductive via is in the second via opening. the second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.

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