Taiwan semiconductor manufacturing company, ltd. (20240178133). PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract
Contents
- 1 PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
Organization Name
taiwan semiconductor manufacturing company, ltd.
Inventor(s)
Hsien-Wei Chen of Hsinchu City (TW)
An-Jhih Su of Taoyuan City (TW)
Li-Hsien Huang of Hsinchu County (TW)
PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240178133 titled 'PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
Simplified Explanation
The abstract of the patent application describes a device package structure with specific features, including a die encapsulated by an encapsulant, a conductive structure, and a dielectric layer with an opening exposing the conductive structure.
- The device includes a die encapsulated by an encapsulant.
- A conductive structure is located beside the die.
- A dielectric layer overlies the conductive structure.
- The conductive structure includes a through via, a redistribution line layer, and a seed layer.
- The dielectric layer has an opening with a scallop sidewall and an included angle larger than 60 degrees.
Potential Applications
The technology described in this patent application could be applied in the semiconductor industry for advanced packaging solutions, such as in microelectronics and integrated circuits.
Problems Solved
This technology addresses the need for improved device packaging structures that provide enhanced performance and reliability in electronic devices.
Benefits
The benefits of this technology include improved electrical connectivity, reduced signal interference, and increased overall device durability and longevity.
Potential Commercial Applications
- Advanced semiconductor packaging solutions for consumer electronics
- High-performance computing applications in data centers
Possible Prior Art
One possible prior art for this technology could be similar device packaging structures with through vias and dielectric layers, but without the specific features described in this patent application.
What materials are used in the conductive structure of the device package?
The conductive structure includes a through via, a redistribution line layer, and a seed layer, but the specific materials used are not mentioned in the abstract.
How does the included angle of the opening in the dielectric layer impact the device performance?
The abstract mentions that the included angle between the bottom surface of the dielectric layer and the sidewall of the opening is larger than 60 degrees, but it does not explain how this angle affects the device's functionality or performance.
Original Abstract Submitted
device, package structure and method of forming the same are disclosed. the device includes a die encapsulated by an encapsulant, a conductive structure aside the die, and a dielectric layer overlying the conductive structure. the conductive structure includes a through via in the encapsulant, a redistribution line layer overlying the through via, and a seed layer overlying the redistribution line layer. the dielectric layer includes an opening, wherein the opening exposes a surface of the conductive structure, the opening has a scallop sidewall, and an included angle between a bottom surface of the dielectric layer and a sidewall of the opening is larger than about 60 degrees.
