Taiwan semiconductor manufacturing company, ltd. (20240178091). Integrated Circuit Package and Method simplified abstract

Integrated Circuit Package and Method

Organization Name

taiwan semiconductor manufacturing company, ltd.

Inventor(s)

Tzu-Sung Huang of Tainan (TW)

Ming Hung Tseng of Toufen Township (TW)

Yen-Liang Lin of Taichung (TW)

Hao-Yi Tsai of Hsinchu (TW)

Chi-Ming Tsai of New Taipei (TW)

Chung-Shi Liu of Hsinchu (TW)

Chih-Wei Lin of Zhubei (TW)

Ming-Che Ho of Tainan (TW)

Integrated Circuit Package and Method - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240178091 titled 'Integrated Circuit Package and Method

Simplified Explanation

The abstract describes a device with an integrated circuit die surrounded by an encapsulant containing fillers, a through via with a decreasing width, and a redistribution structure with a dielectric layer and metallization pattern.

• Integrated circuit die enclosed in an encapsulant with fillers of a certain diameter.
• Through via extending through the encapsulant with a decreasing width.
• Redistribution structure with a dielectric layer and metallization pattern electrically coupled to the integrated circuit die.

Potential Applications

This technology could be applied in the manufacturing of advanced electronic devices such as smartphones, tablets, and computers.

Problems Solved

This innovation helps in improving the electrical connectivity and signal transmission within electronic devices, enhancing their overall performance and reliability.

Benefits

The benefits of this technology include increased efficiency, reduced signal interference, and enhanced durability of electronic devices.

Potential Commercial Applications

• Enhancing the performance of consumer electronics
• Improving the reliability of communication devices

Possible Prior Art

One possible prior art could be the use of through vias in electronic devices to improve signal transmission and connectivity.

How does this technology impact the overall size of electronic devices?

This article does not address how the implementation of this technology affects the physical dimensions of electronic devices.

What are the potential cost implications of integrating this technology into electronic devices?

The article does not discuss the potential cost factors associated with incorporating this technology into the manufacturing process of electronic devices.

Original Abstract Submitted

in an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.