Taiwan semiconductor manufacturing company, ltd. (20240106425). DELAY-LOCKED LOOP CIRCUIT AND METHOD simplified abstract
Contents
- 1 DELAY-LOCKED LOOP CIRCUIT AND METHOD
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 DELAY-LOCKED LOOP CIRCUIT AND METHOD - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
DELAY-LOCKED LOOP CIRCUIT AND METHOD
Organization Name
taiwan semiconductor manufacturing company, ltd.
Inventor(s)
Chung-Peng Hsieh of Hsinchu (TW)
Chih-Chiang Chang of Hsinchu (TW)
Yung-Chow Peng of Hsinchu (TW)
DELAY-LOCKED LOOP CIRCUIT AND METHOD - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240106425 titled 'DELAY-LOCKED LOOP CIRCUIT AND METHOD
Simplified Explanation
A delay-locked loop (DLL) circuit consists of a low pass filter connected to a phase detector, and a digitally controlled delay line (DCDL) connected to the low pass filter. The DCDL includes stages that propagate a signal along different paths to control the delay.
- The DCDL includes stages with inverters that selectively propagate the signal along different paths.
- Each stage includes inverters that control the signal propagation along the first and second paths.
- The stages in the DCDL allow for precise control of the delay of the signal.
- The DCDL is used to synchronize the phase of the input signal with the reference signal.
Potential Applications
The technology can be used in:
- Communication systems
- Data transmission systems
- Radar systems
Problems Solved
The technology helps in:
- Achieving precise synchronization of signals
- Minimizing phase noise
- Improving signal integrity
Benefits
The benefits of this technology include:
- Improved signal quality
- Reduced jitter
- Enhanced system performance
Potential Commercial Applications
The technology can be applied in:
- Telecommunication equipment
- Test and measurement devices
- Networking devices
Possible Prior Art
One possible prior art for this technology is the use of delay-locked loops in communication systems to synchronize signals.
Unanswered Questions
How does the circuit handle variations in input signal frequency?
The article does not provide information on how the circuit adapts to changes in input signal frequency.
What is the power consumption of the circuit compared to traditional delay-locked loops?
The article does not address the power consumption aspect of the circuit in comparison to traditional delay-locked loops.
Original Abstract Submitted
a delay-locked loop (dll) circuit includes a low pass filter coupled to a phase detector, and a digitally controlled delay line (dcdl) coupled to the low pass filter. the dcdl includes an input terminal, an output terminal coupled to an input terminal of the phase detector, and stages that propagate a signal along a first path from the input terminal to a selectable return stage and along a second path from the return stage to the output terminal. each stage includes first and second inverters that selectively propagate the signal along the first and second paths, a third inverter that selectively propagates the signal from the first path to the second path, and either fourth and fifth inverters that selectively propagate the signal along the first and second paths, or a sixth inverter that selectively propagates the signal from the first path to the second path.
