Taiwan semiconductor manufacturing company, ltd. (20240105644). SEMICONDUCTOR DIE PACKAGE AND METHODS OF FORMATION simplified abstract

SEMICONDUCTOR DIE PACKAGE AND METHODS OF FORMATION

Organization Name

taiwan semiconductor manufacturing company, ltd.

Inventor(s)

Tsung-Hao Yeh of Hsinchu City (TW)

Chien Hung Liu of Hsinchu County (TW)

Hsien Jung Chen of Tainan City (TW)

Hsin Heng Wang of Hsinchu County (TW)

Kuo-Ching Huang of Hsinchu City (TW)

SEMICONDUCTOR DIE PACKAGE AND METHODS OF FORMATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240105644 titled 'SEMICONDUCTOR DIE PACKAGE AND METHODS OF FORMATION

Simplified Explanation

The semiconductor die package described in the patent application includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (WOW) configuration. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. This helps reduce current leakage in semiconductor devices included in the device region.

• High dielectric constant (high-k) dielectric layer over device region of first semiconductor die
• Intrinsic negative charge polarity in high-k dielectric layer provides coupling voltage to modify electric potential
• Reduces current leakage in semiconductor devices in device region
• Through Silicon Via (TSV) structure may be formed through the device region
• Electron carriers in high-k dielectric layer attract hole charge carriers in device region, suppressing trap-assist tunnels
• Reduces likelihood and magnitude of current leakage in semiconductor devices

Potential Applications

The technology described in the patent application could be applied in various semiconductor devices where reducing current leakage is crucial, such as in high-performance computing, telecommunications equipment, and power electronics.

Problems Solved

This technology addresses the issue of current leakage in semiconductor devices, which can lead to reduced performance, increased power consumption, and potential device failure.

Benefits

The high dielectric constant (high-k) dielectric layer helps improve the reliability and efficiency of semiconductor devices by reducing current leakage and suppressing trap-assist tunnels, ultimately enhancing overall device performance.

Potential Commercial Applications

The technology could be utilized in the manufacturing of advanced semiconductor devices for industries such as consumer electronics, automotive, aerospace, and medical devices.

Possible Prior Art

One possible prior art could be the use of different dielectric materials to reduce current leakage in semiconductor devices. However, the specific approach of using a high dielectric constant (high-k) dielectric layer with an intrinsic negative charge polarity as described in this patent application may be a novel innovation in the field.

Original Abstract Submitted

a semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (wow) configuration. a through silicon via (tsv) structure may be formed through the device region. the high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. in particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the tsv structure. accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.