Taiwan semiconductor manufacturing co., ltd. (20240250061). WAFER BONDING METHOD simplified abstract
Contents
WAFER BONDING METHOD
Organization Name
taiwan semiconductor manufacturing co., ltd.
Inventor(s)
Yung-Chi Lin of Su-Lin City (TW)
Wen-Chih Chiou of Zhunan Township (TW)
WAFER BONDING METHOD - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240250061 titled 'WAFER BONDING METHOD
The abstract describes a device with two wafers bonded together, each containing a substrate and an interconnect structure with specific angles and offsets.
- First wafer with a first substrate and interconnect structure forming an obtuse angle.
- Second wafer bonded to the first wafer with a second substrate and interconnect structure.
- Lateral offset between the sidewalls of the first and second substrates and interconnect structures.
Potential Applications: - Semiconductor manufacturing - Microelectronics industry - Integrated circuit fabrication
Problems Solved: - Enhanced device performance - Improved signal transmission - Increased device reliability
Benefits: - Higher efficiency in electronic devices - Better connectivity between components - Compact design for space-saving solutions
Commercial Applications: Title: Advanced Semiconductor Devices for Enhanced Performance This technology can be used in the production of high-performance electronic devices such as smartphones, computers, and IoT devices, improving their overall functionality and reliability in various industries.
Questions about the technology: 1. How does the lateral offset between the substrates and interconnect structures impact device performance? 2. What are the specific advantages of bonding two wafers with different angles and offsets in semiconductor manufacturing?
Original Abstract Submitted
in an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.
