Taiwan semiconductor manufacturing co., ltd. (20240222247). SOLDER RESIST STRUCTURE TO MITIGATE SOLDER BRIDGE RISK simplified abstract
Contents
SOLDER RESIST STRUCTURE TO MITIGATE SOLDER BRIDGE RISK
Organization Name
taiwan semiconductor manufacturing co., ltd.
Inventor(s)
Chin-Hua Wang of New Taipei City (TW)
Shu-Shen Yeh of Taoyuan City (TW)
Po-Chen Lai of Hsinchu County (TW)
Po-Yao Lin of Zhudong Township (TW)
SOLDER RESIST STRUCTURE TO MITIGATE SOLDER BRIDGE RISK - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240222247 titled 'SOLDER RESIST STRUCTURE TO MITIGATE SOLDER BRIDGE RISK
The semiconductor structure in this patent application includes a substrate with conductive pads and conductive bumps on the pads, as well as a multi-tiered solder-resist structure with specific dimensions.
- The first tier of the solder-resist structure contains a dielectric material and conductive bump openings with a certain width.
- The second tier, which overlays the first tier, also contains a dielectric material and conductive bump openings with a different width.
- The ratio of the width of the first tier to the width of the second tier falls within a specific range.
Potential Applications: - This technology could be used in the manufacturing of semiconductor devices to improve their performance and reliability. - It may find applications in various electronic devices where precise control of conductive paths is essential.
Problems Solved: - Provides a more precise and controlled method for creating conductive paths on semiconductor structures. - Helps in reducing the risk of short circuits and other electrical failures in electronic devices.
Benefits: - Enhanced performance and reliability of semiconductor devices. - Improved manufacturing processes for electronic components.
Commercial Applications: Title: Advanced Semiconductor Structure for Enhanced Performance This technology could be utilized in the production of high-performance electronic devices, such as smartphones, tablets, and computers, to improve their overall functionality and durability.
Questions about the technology: 1. How does the specific ratio of widths in the solder-resist structure contribute to the overall performance of the semiconductor device? 2. What are the potential cost implications of implementing this technology in mass production processes?
Original Abstract Submitted
some embodiments relate to a semiconductor structure including a substrate with conductive pads and conductive bumps disposed on the conductive pads, respectively. a multi-tiered solder-resist structure includes a first tier and a second tier. the first tier includes a first dielectric material and first conductive bump openings defined by inner sidewalls of the first tier. the first tier has a first width measured through the first dielectric material between the inner sidewalls of the first tier in a cross-sectional view. the second tier overlies the first tier and includes a second dielectric material and second conductive bump openings defined by inner sidewalls of the second tier. the second tier has a second width measured through the second dielectric material between the inner sidewalls of the second tier in the cross-sectional view. a ratio of the first width to the second width ranges from 1.1:1 to 2:1.
