Taiwan semiconductor manufacturing co., ltd. (20240222196). METAL GATE PATTERNING simplified abstract

METAL GATE PATTERNING

Organization Name

taiwan semiconductor manufacturing co., ltd.

Inventor(s)

Tefu Yeh of Kaohsiung (TW)

Cheng-Chieh Tu of Hsinchu (TW)

Hao-Hsin Chen of Keelung (TW)

Jo-Chun Hung of Hsinchu (TW)

Ying-Liang Chuang of Hsinchu (TW)

Ming-Hsi Yeh of Hsinchu (TW)

Kuo-Bin Huang of Hsinchu (TW)

METAL GATE PATTERNING - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240222196 titled 'METAL GATE PATTERNING

The method described in the patent application involves forming gate structures for n-type and p-type transistors using a series of steps including the use of interfacial and high-k dielectric layers, metal layers, hard capping layers, and fluorine passivation.

• Forming an interfacial layer and high-k dielectric layer for the gate structures
• Depositing an n-type metal layer over the high-k dielectric layer
• Applying a hard capping layer over the n-type metal layer while simultaneously strengthening the high-k dielectric layer with fluorine passivation
• Patterning photo resist material over the hard capping layer to expose a portion over the p-type transistor
• Removing the n-type metal layer and hard capping layer over the p-type transistor through wet etching operations with high selectivity chemicals
• Insulating gate structures from aluminum oxidation by removing the patterned photo resist material
• Depositing a p-type metal layer over the hard capping layer and the p-type transistor

Potential Applications: - Semiconductor manufacturing - Integrated circuit fabrication - Electronics industry

Problems Solved: - Enhancing the performance and reliability of transistors - Improving the efficiency of semiconductor devices - Reducing gate leakage in transistors

Benefits: - Increased transistor performance - Enhanced device reliability - Improved manufacturing processes

Commercial Applications: Title: Advanced Gate Structure Formation Method for Semiconductor Devices This technology can be utilized in the production of high-performance electronic devices, leading to improved efficiency and reliability in various applications such as smartphones, computers, and automotive electronics.

Questions about the technology: 1. How does the use of fluorine passivation contribute to the strengthening of the high-k dielectric layer? 2. What are the specific advantages of using a hard capping layer in the formation of gate structures for transistors?

Original Abstract Submitted

disclosed is a method of forming gate structures for n-type and p-type transistors. the method includes: forming an interfacial layer and high-k (hk) dielectric layer for the gate structures; forming an n-type metal layer over the hk dielectric layer; forming a hard capping layer over the n-type metal layer while simultaneously strengthening the hk dielectric layer by fluorine passivation; patterning photo resist (pr) material over the hard capping layer that exposes a portion of the hard capping layer over the p-type transistor; removing the n-type metal layer and the hard capping layer over the p-type transistor via wet etching operations using high selectivity chemicals that are highly selective to the hard capping layer and the n-type metal layer; removing the patterned pr material while insulating, by the hard capping layer, gate structures from aluminum oxidation; and forming a p-type metal layer over the hard capping layer and the p-type transistor.