Taiwan semiconductor manufacturing co., ltd. (20240194480). Methods of Reducing Gate Spacer Loss During Semiconductor Manufacturing simplified abstract
Contents
Methods of Reducing Gate Spacer Loss During Semiconductor Manufacturing
Organization Name
taiwan semiconductor manufacturing co., ltd.
Inventor(s)
Yi-Ruei Jhan of Keelung City (TW)
Han-Yu Lin of Nantou County (TW)
Pinyen Lin of Rochester NY (US)
Methods of Reducing Gate Spacer Loss During Semiconductor Manufacturing - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240194480 titled 'Methods of Reducing Gate Spacer Loss During Semiconductor Manufacturing
Simplified Explanation: The patent application describes a method involving the formation of a dummy gate structure on a semiconductor substrate, followed by the creation of a gate spacer on the dummy gate structure's sidewall. Subsequent implantation processes are then carried out using different dosage sources to modify the gate spacer.
- The method involves forming a dummy gate structure on a semiconductor substrate.
- A gate spacer is then formed on the sidewall of the dummy gate structure.
- A first implantation process is performed on the upper portion of the gate spacer using a first dosage source.
- A second implantation process is carried out on the upper portion of the gate spacer using a second dosage source containing carbon.
- The second dosage source is distinct from the first dosage source.
Potential Applications: This technology could be applied in the semiconductor industry for the fabrication of advanced transistors with tailored properties.
Problems Solved: This method addresses the need for precise control over the doping of gate spacers in semiconductor devices to enhance their performance.
Benefits: The method allows for the customization of gate spacer properties, leading to improved transistor characteristics and overall device performance.
Commercial Applications: Title: Advanced Semiconductor Transistor Fabrication Method This technology could be utilized in the production of high-performance semiconductor devices for various applications such as consumer electronics, telecommunications, and computing.
Prior Art: Researchers can explore existing literature on semiconductor device fabrication techniques, gate spacer doping methods, and transistor performance optimization.
Frequently Updated Research: Ongoing research in semiconductor materials and device engineering may offer new insights into optimizing gate spacer doping processes for enhanced transistor performance.
'Questions about Semiconductor Transistor Fabrication Method: 1. How does the use of different dosage sources in the implantation processes impact the properties of the gate spacer? 2. What are the potential challenges associated with implementing this method in large-scale semiconductor manufacturing processes?
Original Abstract Submitted
a method includes forming a dummy gate structure over a semiconductor substrate, forming a gate spacer over a sidewall of the dummy gate structure, performing a first implantation process to an upper portion of the gate spacer using a first dosage source, and performing a second implantation process to the upper portion of the gate spacer using a second dosage source including carbon. the second dosage source is different from the first dosage source.
