Taiwan semiconductor manufacturing co., ltd. (20240186283). INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF simplified abstract

INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF

Organization Name

taiwan semiconductor manufacturing co., ltd.

Inventor(s)

Jhih-Yu Wang of New Taipei City (TW)

Hung-Jui Kuo of Hsinchu City (TW)

Yu-Hsiang Hu of Hsinchu City (TW)

Sih-Hao Liao of New Taipei City (TW)

Yung-Chi Chu of Kaohsiung City (TW)

INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240186283 titled 'INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF

Simplified Explanation

An integrated fan-out package consists of a die, an encapsulant surrounding the die, and a redistribution structure on the encapsulant. The redistribution structure includes routing patterns and alignment marks, with the routing patterns connected to the die and the alignment marks surrounding them. The alignment marks are insulated from the die and routing patterns, with some in physical contact with the encapsulant and arranged vertically without overlapping.

• The package includes a die, encapsulant, and redistribution structure.
• The redistribution structure has routing patterns and alignment marks.
• Alignment marks are insulated from the die and routing patterns.
• Some alignment marks are in physical contact with the encapsulant.
• Alignment marks at different heights are arranged vertically without overlapping.

Potential Applications

This technology can be used in semiconductor packaging, integrated circuits, and electronic devices where precise alignment and electrical connections are crucial.

Problems Solved

This innovation addresses the challenges of aligning and connecting components in a compact and efficient manner, ensuring reliable performance in electronic devices.

Benefits

The benefits of this technology include improved electrical connections, precise alignment, and enhanced reliability in semiconductor packaging and electronic devices.

Commercial Applications

• Semiconductor packaging industry
• Integrated circuit manufacturing
• Consumer electronics market

Prior Art

There are existing technologies in the field of semiconductor packaging and integrated circuits that focus on improving alignment and electrical connections, but this specific integration of alignment marks and routing patterns is a novel approach.

Frequently Updated Research

Ongoing research in semiconductor packaging and integrated circuits may lead to further advancements in alignment and connection technologies, enhancing the performance and reliability of electronic devices.

Unanswered Questions

Question 1

How does the arrangement of alignment marks at different heights without overlapping improve the performance of the integrated fan-out package?

Answer 1

The non-overlapping arrangement of alignment marks at different heights allows for precise alignment and electrical insulation, ensuring reliable connections and performance in the package.

Question 2

What are the potential challenges in scaling up this technology for mass production in the semiconductor industry?

Answer 2

Scaling up this technology for mass production may involve optimizing manufacturing processes, ensuring consistency in alignment and electrical connections, and addressing any potential issues in yield and cost-effectiveness.

Original Abstract Submitted

an integrated fan-out (info) package includes a die, an encapsulant laterally encapsulating the die, and a redistribution structure. the redistribution structure is disposed on the encapsulant. the redistribution structure includes a plurality of routing patterns and a plurality of alignment marks. the routing patterns are electrically connected to the die. the alignment marks surround the routing patterns. the alignment marks are electrically insulated from the die and the routing patterns. at least one of the alignment marks is in physical contact with the encapsulant, and the alignment marks located at different level heights are arranged in a non-overlapping manner vertically.