Taiwan semiconductor manufacturing co., ltd. (20240162349). GATE RESISTANCE REDUCTION THROUGH LOW-RESISTIVITY CONDUCTIVE LAYER simplified abstract

GATE RESISTANCE REDUCTION THROUGH LOW-RESISTIVITY CONDUCTIVE LAYER

Organization Name

taiwan semiconductor manufacturing co., ltd.

Inventor(s)

Chung-Chiang Wu of Taichung City (TW)

Po-Cheng Chen of Jiaoxi Township (TW)

Kuo-Chan Huang of Hsinchu (TW)

Hung-Chin Chung of Pingzhen City (TW)

Hsien-Ming Lee of Changhua (TW)

Chien-Hao Chen of Chuangwei Township (TW)

GATE RESISTANCE REDUCTION THROUGH LOW-RESISTIVITY CONDUCTIVE LAYER - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240162349 titled 'GATE RESISTANCE REDUCTION THROUGH LOW-RESISTIVITY CONDUCTIVE LAYER

Simplified Explanation

The patent application describes a device with a semiconductor fin and a gate stack on the sidewalls and top surface of the fin. The gate stack includes a high-k dielectric layer, a work-function layer, a blocking layer, and a low-resistance metal layer.

• The device includes a semiconductor fin and a gate stack.
• The gate stack consists of a high-k dielectric layer, a work-function layer, a blocking layer, and a low-resistance metal layer.
• The low-resistance metal layer has a resistivity value lower than the work-function layer and the blocking layer.
• A gate spacer contacts the sidewall of the gate stack.

Potential Applications

This technology could be applied in the development of advanced semiconductor devices, such as high-performance transistors for various electronic applications.

Problems Solved

This technology helps in improving the performance and efficiency of semiconductor devices by reducing resistivity and enhancing gate control.

Benefits

The benefits of this technology include enhanced device performance, reduced power consumption, and improved overall efficiency in electronic devices.

Potential Commercial Applications

The potential commercial applications of this technology could include the production of faster and more energy-efficient electronic devices for consumer electronics, telecommunications, and computing industries.

Possible Prior Art

Prior art in the field of semiconductor device fabrication may include similar techniques for improving gate stack structures and reducing resistivity in semiconductor devices.

How does this technology impact the overall cost of semiconductor device production?

This article does not address the potential cost implications of implementing this technology in semiconductor device manufacturing processes.

What are the environmental implications of using low-resistance metal layers in semiconductor devices?

The article does not discuss the environmental impact of incorporating low-resistance metal layers in semiconductor devices.

Original Abstract Submitted

a device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. the gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. a low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. the low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. a gate spacer contacts a sidewall of the gate stack.