Taiwan semiconductor manufacturing co., ltd. (20240162183). DIE ATTACHED LEVELING CONTROL BY METAL STOPPER BUMPS simplified abstract
Contents
- 1 DIE ATTACHED LEVELING CONTROL BY METAL STOPPER BUMPS
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 DIE ATTACHED LEVELING CONTROL BY METAL STOPPER BUMPS - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
DIE ATTACHED LEVELING CONTROL BY METAL STOPPER BUMPS
Organization Name
taiwan semiconductor manufacturing co., ltd.
Inventor(s)
Wei-Jhih Mao of Taipei City (TW)
Kuei-Sung Chang of Kaohsiung City (TW)
Shang-Ying Tsai of Pingzhen City (TW)
DIE ATTACHED LEVELING CONTROL BY METAL STOPPER BUMPS - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240162183 titled 'DIE ATTACHED LEVELING CONTROL BY METAL STOPPER BUMPS
Simplified Explanation
The present disclosure is about an integrated chip with a substrate and a first die, along with die stopper bumps and adhesive structures for securing the components together.
- The integrated chip includes a substrate and a first die.
- A first plurality of die stopper bumps are placed along the backside of the first die.
- The die stopper bumps directly contact the backside of the first die and are arranged in groups.
- Adhesive structures surround each group of die stopper bumps to provide additional support.
Potential Applications
This technology could be used in various electronic devices such as smartphones, tablets, and computers where compact and secure chip integration is required.
Problems Solved
1. Ensures proper alignment and connection between the substrate and the first die. 2. Prevents damage to the components during handling and operation.
Benefits
1. Improved reliability and durability of the integrated chip. 2. Enhanced performance due to secure component placement. 3. Simplified manufacturing process with the use of die stopper bumps and adhesive structures.
Potential Commercial Applications
Optimizing Chip Integration for Enhanced Performance
Possible Prior Art
There are existing methods for securing dies to substrates in integrated chips, but the specific arrangement of die stopper bumps and adhesive structures as described in this disclosure may be novel.
Unanswered Questions
How does this technology compare to traditional methods of securing dies to substrates in integrated chips?
This technology offers a more organized and secure way of aligning and connecting components compared to traditional methods, potentially leading to improved performance and reliability.
What are the potential challenges in implementing this technology on a larger scale in manufacturing processes?
One challenge could be ensuring the precise placement of die stopper bumps and adhesive structures on a mass production scale without compromising efficiency or cost-effectiveness.
Original Abstract Submitted
in some embodiments, the present disclosure relates to an integrated chip including a substrate and a first die disposed over the substrate. a first plurality of die stopper bumps are disposed along a backside of the first die. the first plurality of die stopper bumps directly contact the backside of the first die, and the first plurality of die stopper bumps are arranged as a plurality of groups of die stopper bumps. a plurality of adhesive structures are also present. each of the plurality of adhesive structures surrounds a corresponding group of the plurality of groups of die stopper bumps.
