Taiwan semiconductor manufacturing co., ltd. (20240161803). FERROELECTRIC MEMORY OPERATION BIAS AND POWER DOMAINS simplified abstract

FERROELECTRIC MEMORY OPERATION BIAS AND POWER DOMAINS

Organization Name

taiwan semiconductor manufacturing co., ltd.

Inventor(s)

Katherine H. Chiang of New Taipei City (TW)

Chung-Te Lin of Tainan City (TW)

FERROELECTRIC MEMORY OPERATION BIAS AND POWER DOMAINS - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240161803 titled 'FERROELECTRIC MEMORY OPERATION BIAS AND POWER DOMAINS

Simplified Explanation

The memory system described in the abstract consists of memory cells, word lines, bit lines, and source lines arranged in rows and columns. During a write operation, specific voltages are applied to the word line, bit line, and source line of a selected memory cell.

• Memory system components:

 - Memory cells with gates, drains, and sources
 - Word lines connected to memory cell gates
 - Bit lines connected to memory cell drains
 - Source lines connected to memory cell sources

• Write operation:

 - Word line receives a first voltage
 - Bit line and source line of selected memory cell receive a second voltage
 - Voltages can be positive or negative

Potential Applications

The memory system can be used in various electronic devices such as computers, smartphones, and IoT devices for data storage and retrieval.

Problems Solved

1. Efficient data storage and retrieval in electronic devices 2. Improved memory cell addressing and voltage application during write operations

Benefits

1. Faster data processing and access times 2. Higher data storage capacity 3. Enhanced reliability and durability of memory cells

Potential Commercial Applications

Optimizing memory systems for consumer electronics SEO optimized title: "Commercial Applications of Advanced Memory Systems"

Possible Prior Art

Prior art may include existing memory systems with similar configurations and voltage application methods.

How does the memory system handle read operations?

The abstract only mentions write operations, so it is unclear how the memory system functions during read operations.

What are the specific voltage levels used in the write operation?

The abstract mentions applying a first and second voltage, but does not specify the exact voltage levels used in the process.

Original Abstract Submitted

a memory system including a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a plurality of source lines. the plurality of memory cells are arranged in rows and columns, each of the plurality of memory cells having a gate, a drain, and a source. in the plurality of word lines, each of the word lines having a corresponding row, wherein each of the word lines is coupled to the gates of the memory cells in the corresponding row. in the plurality of bit lines and the plurality of source lines, each of the bit lines and each of the source lines having a corresponding column, where each of the bit lines is connected to the drain of the memory cells in the corresponding column and each of the source lines is connected to the source of the memory cells in the corresponding column. where, in a write operation, the word line corresponding to a selected memory cell is configured to receive a first voltage, and the bit line and the source line of the selected memory cell are configured to receive a second voltage, and where one of the first voltage or the second voltage is a positive voltage and the other of the first voltage or the second voltage is a negative voltage.