Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on June 27th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on June 27th, 2024
Taiwan Semiconductor Manufacturing Company, Ltd.: 52 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L23/00 (12), H01L29/06 (10), H01L29/66 (10), H01L23/522 (8), H01L21/8234 (7) H01L25/18 (2), H10B61/22 (2), G01K1/20 (1), H01L29/0653 (1), H01L23/66 (1)
With keywords such as: layer, semiconductor, structure, device, gate, dielectric, memory, substrate, disposed, and coupled in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s): Feng-Wei KUO of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Shiang Liao of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/12, G02B6/293
CPC Code(s): G02B6/12007
Abstract: a thermally tunable waveguide including an optical waveguide and a heater is provided. the optical waveguide includes a phase shifter. the heater is disposed over the optical waveguide. the heater includes a heating portion, pad portions and tapered portions. the heating portion overlaps with the phase shifter of the optical waveguide. the pad portions are disposed aside of the heating portion. each of the pad portions is connected to the heating portion through one of the tapered portions respectively.
Inventor(s): Feng-Wei KUO of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chewn-Pu JOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Kuo Hsia of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/12, G02B6/124, G02B6/132, H01S5/026
CPC Code(s): G02B6/12019
Abstract: a device includes a dielectric layer, a plurality of grating structures, and a dielectric material between the plurality of grating structures and on top of the plurality of grating structures. the grating structures are arranged on the dielectric layer and separated from each other, the plurality of grating structures each having a bottom portion and top portion, the top portion having a first width and the bottom portion having a second width, the second width being larger than the first width.
Inventor(s): Feng-Wei KUO of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Kuo HSIA of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chewn-Pu JOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/30, G02B6/12, G02B6/124, G02B6/32, G02B6/34
CPC Code(s): G02B6/30
Abstract: a device for optical signal processing includes a first layer, a second layer and a waveguiding layer. a lens is disposed within the first layer and adjacent to a surface of the first layer. the second layer is underneath the first layer and adjacent to another surface of the first layer. the waveguiding layer is located underneath the second layer and configured to waveguide a light beam transmitted in the waveguiding layer. a grating coupler is disposed over the waveguiding layer. the lens is configured to receive, from one of the grating coupler or a light-guiding element, the light beam, and focus the light beam towards another one of the light-guiding element or the grating coupler.
Inventor(s): Hsien-Wei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jie Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42, H01L21/48, H01L23/498
CPC Code(s): G02B6/4202
Abstract: a semiconductor package includes a semiconductor die, a device layer over the semiconductor die and including an optical device, an insulator layer over the device layer, a buffer layer over the insulator layer, an etch stop layer between the device layer and the insulator layer, a connective terminal, and a bonding via passing through the device layer and electrically connecting the semiconductor die to the connective terminal. the conductive terminal passes through the etch stop layer, the insulator layer, and the buffer layer. the conductive terminal is in direct contact with the etch stop layer.
20240210636.PACKAGE STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Chung-Ming Weng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Shi Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chieh Hsieh of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Yi Kuo of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yuan Yu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hua-Kuei Lin of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Che-Hsiang Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42, H01L23/00
CPC Code(s): G02B6/4243
Abstract: a package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. the photonic die includes an optical coupler. the electronic die is electrically coupled to the photonic die. the encapsulant laterally encapsulates the photonic die and the electronic die. the waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. the waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.
Inventor(s): An-Ren Zi of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/004, G03F7/09, H01L21/308
CPC Code(s): G03F7/0044
Abstract: a method for forming a semiconductor device is provided. the method includes forming a coating layer over a substrate, the coating layer comprising a switchable polymer comprising a polymer backbone and pendant groups attached to the polymer backbone and an acid generator. the pendant groups include acid labile groups and crosslinking groups. a baking process is then performed to cause crosslinking of the crosslinking groups to form a crosslinked coating layer. next, a photoresist layer is deposited over the crosslinked coating layer. after selectively exposing the photoresist layer and the crosslinked coating layer to a patterning radiation, the selectively exposed photoresist layer and the crosslinked coating layer are developed to form a pattern of openings in the photoresist layer and the crosslinked coating layer.
Inventor(s): Shih-Yu TU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Hua WANG of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Hao LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chueh-Chi KUO of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jui CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Heng-Hsin LIU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00
CPC Code(s): G03F7/70925
Abstract: in a method of cleaning a lithography system, during idle mode, a stream of air is directed, through a first opening, into a chamber of a wafer table of an euv lithography system. one or more particles is extracted by the directed stream of air from surfaces of one or more wafer chucks in the chamber of the wafer table. the stream of air and the extracted one or more particle are drawn, through a second opening, out of the chamber of the wafer table.
Inventor(s): Tsung-Che LU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Ming FU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hsien CHANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/06, G11C5/14, G11C7/10, G11C7/14
CPC Code(s): G11C7/062
Abstract: a sense amplifier includes a first pair of transistors having gate terminals respectively coupled to a first input terminal for receiving a first input signal and to a second input terminal for receiving a second input signal, source terminals coupled to a first power supply terminal, and drain terminals. the sense amplifier also includes a second pair of transistors having gate terminals coupled to a clock terminal, source terminals respectively coupled to the drain terminals of the first pair of transistors, and drain terminals. the sense amplifier also includes a third pair of transistors having gate terminals coupled to the clock terminal, drain terminals respectively coupled to the drain terminals of the second pair of transistors, and source terminals coupled to a second power supply terminal. in addition, the sense amplifier includes an output circuit coupled to the drain terminals of the second pair of transistors and having an output terminal.
20240212727.MEMORY DEVICE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Meng-Sheng CHANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En HUANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ching LIU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yih WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/10, G11C7/12, G11C7/18, G11C8/08, G11C8/14
CPC Code(s): G11C7/1051
Abstract: a memory device includes a plurality of arrays coupled in parallel with each other. a first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. the second switch is configured to output a data signal from the at least one data line to a sense amplifier.
Inventor(s): Chia-Che CHUNG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Jung TSEN of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ya-Jui TSOU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chee-Wee LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/16, H03K19/1776
CPC Code(s): G11C11/1673
Abstract: a device is provided. the device includes a physical unclonable function (puf) cell array. the puf cell array includes multiple bit cells, and generates a puf response output, in response to a challenge input, based on a data state of one bit cell in the bit cells. each of the bit cells stores a bit data and includes a transistor having a control terminal coupled to a word line and a first terminal coupled to a source line, a first memory cell having a first terminal coupled to a first data line and a second terminal coupled to a second terminal of the transistor, and a second memory cell having a first terminal coupled to a second data line, different from the first data line, and a second terminal coupled to the second terminal of the first memory cell at the second terminal of the transistor.
Inventor(s): Atul Katoch of Kanata (CA) for taiwan semiconductor manufacturing company, ltd., Adrian Earle of Ontario (CA) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/4094, G11C11/4074, G11C11/4096, G11C11/411, G11C11/419
CPC Code(s): G11C11/4094
Abstract: a memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. a bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.
Inventor(s): Hidehiro Fujiwara of Hsin-chu (TW) for taiwan semiconductor manufacturing company, ltd., Kao-Cheng Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei Min Chan of Sindian City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Huei Chen of Jhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/418, G11C11/412, G11C11/419, H03K17/687
CPC Code(s): G11C11/418
Abstract: a device includes a first power rail for a first power domain and a second power rail for a second power domain. a first circuit block is connected to the first power rail and a second circuit block is connected to the second power rail. the first and second circuit blocks are both connected to a virtual vss terminal. a footer circuit is connected between the virtual vss terminal and a ground terminal, and the footer circuit is configured to selectively control a connection between the virtual vss terminal and the ground terminal.
Inventor(s): Yi-Hsin Nien of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hidehiro Fujiwara of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yu Lin of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Huei Chen of Jhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/419
CPC Code(s): G11C11/419
Abstract: a memory device and a method for operating the memory device are provided. the memory device includes a memory cell and a bit line connected to the memory cell. a negative voltage generator is connected to the bit line. the negative voltage generator, when enabled, is operative to provide a first write path for the bit line. a control circuit is connected to the negative voltage generator and the bit line. the control circuit is operative to provide a second write path for the bit line when the negative voltage generator is not enabled.
Inventor(s): Meng-Sheng Chang of Chubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En Huang of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd., Yih Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C16/10, G11C16/26, H01L29/06, H01L29/423, H01L29/78
CPC Code(s): G11C16/10
Abstract: a memory system includes a memory array comprising a plurality of memory cells. each of the memory cells includes a first programming transistor, a second programming transistor, a first reading transistor coupled to the first programming transistor in series, and a second reading transistor coupled to the second programming transistor in series. the memory system includes an authentication circuit operatively coupled to the memory array. the authentication circuit is configured to generate a physically unclonable function (puf) signature based on respective logic states of the plurality of memory cells. the logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first programming transistor or second programming transistor.
Inventor(s): Chih-Min LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C17/18, G11C11/16, G11C17/16
CPC Code(s): G11C17/18
Abstract: a circuit includes a plurality of anti-fuse cells coupled to a first selection circuit, a plurality of magnetic random-access memory (mram) cells coupled to a second selection circuit, an amplifier including a first input terminal coupled to each of the first and second selection circuits, an analog-to-digital converter (adc) including input terminals coupled to output terminals of the amplifier, and a comparator including a first input port coupled to an output port of the adc. the amplifier, adc, and comparator are configured to output data bits from the comparator responsive to current levels received from the first selection circuit at the first input terminal of the amplifier and first voltage levels received from the second selection circuit at the first input terminal of the amplifier.
Inventor(s): Cheng-Wei Chang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Min-Hsiu Hung of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-I Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ken-Yu Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ying Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, H01L21/768
CPC Code(s): H01L21/02068
Abstract: a method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. the forming the first conductive feature leaves seeds on sidewalls of the opening. a treatment process is performed on the seeds to form treated seeds. the treated seeds are removed with a cleaning process. the cleaning process may include a rinse with deionized water. a second conductive feature is formed to fill the opening.
Inventor(s): Shih-Ming Chang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Ming Lai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Ju Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ru-Gun Liu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin Shue of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tien-I Bao of Dayuan Township (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Sheng Gau of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/321, H01L21/3105, H01L21/311, H01L21/768, H01L23/522
CPC Code(s): H01L21/3212
Abstract: an integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on the first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.
Inventor(s): Chang-Yun CHANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Bone-Fong WU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Chang WEN of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Ya-Hsiu LIN of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/02, H01L21/027, H01L21/265, H01L21/3105, H01L21/311, H01L21/324, H01L21/762, H01L27/088, H01L29/06, H01L29/08, H01L29/66
CPC Code(s): H01L21/823431
Abstract: a device includes a semiconductor fin, a gate structure, gate spacers, and a dielectric feature. the semiconductor fin is over a substrate. the gate structure is over the semiconductor fin and includes a gate dielectric layer over the semiconductor fin and a gate metal covering the gate dielectric layer. the gate spacers are on opposite sides of the gate structure. the dielectric feature is over the substrate. the dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers.
Inventor(s): Chung-Liang CHENG of Changhua County 500 (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/8238, H01L29/06, H01L29/423, H01L29/786
CPC Code(s): H01L21/823462
Abstract: a semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. the method includes forming first and second nanostructured channel regions on first and second fin structures, forming first and second oxide layers with first and second thicknesses, forming a dielectric layer with first and second layer portions on the first and second oxide layers, forming first and second capping layers with first and second oxygen diffusivities on the first and second layer portions, growing the first and second oxide layers to have third and fourth thicknesses, and forming a gate metal fill layer over the dielectric layer. the first and second thicknesses are substantially equal to each other and the first and second oxide layers surround the first and second nanostructured channel regions. the second oxygen diffusivity is higher than the first oxygen diffusivity. the fourth thickness is greater than the third thickness.
Inventor(s): Jhe-Ching Lu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Sen Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Bao-Ru Young of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Chieh Tsai of Hsin-Chu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L27/092
CPC Code(s): H01L21/823807
Abstract: semiconductor device and the manufacturing method thereof are disclosed. an exemplary method comprises forming a first semiconductor layer including a first semiconductor material in a first area of a substrate; alternately depositing second semiconductor layers and third semiconductor layers over the first semiconductor layer and over the substrate to form a semiconductor layer stack, wherein the second semiconductor layers include a second semiconductor material, the third semiconductor layers include the first semiconductor material, the second semiconductor material is different from the first semiconductor material, and a bottom surface of one of the second semiconductor layers contacts the first semiconductor layer in the first area and contacts the substrate in a second area of the substrate; planarizing a top surface of the semiconductor layer stack; and patterning the semiconductor layer stack to form a first semiconductor structure in the first area and a second semiconductor structure in the second area.
20240213121.3D IC POWER GRID_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Noor E.V. Mohamed of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fong-Yuan Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiang Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Chou Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L21/822, H01L23/00, H01L25/065
CPC Code(s): H01L23/481
Abstract: a three dimensional integrated circuit (ic) power grid (pg) may be provided. the three dimensional ic pg may comprise a first ic die, a second ic die, an interface, and a power distribution structure. the interface may be disposed between the first ic die and the second ic die. the power distribution structure may be connected to the interface. the power distribution structure may comprise at least one through-silicon vias (tsv) and a ladder structure connected to at least one tsv.
Inventor(s): Shin-Yi Yang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Han Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin Shue of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/324, H01L21/768, H01L23/522
CPC Code(s): H01L23/53238
Abstract: interconnect structures and method of forming the same are disclosed herein. an exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.
Inventor(s): Chia-Cheng Chou of Keelung City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Chi Ko of Nantou (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Tsung Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/768
CPC Code(s): H01L23/53295
Abstract: a semiconductor device including a substrate, a low-k dielectric layer, a cap layer, and a conductive layer is provided. the low-k dielectric layer is disposed over the substrate. the cap layer is disposed on the low-k dielectric layer, wherein a carbon atom content of the cap layer is greater than a carbon atom content of the low-k dielectric layer. the conductive layer is disposed in the cap layer and the low-k dielectric layer.
Inventor(s): Chih-Kai CHENG of Chu-dong Villiage (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Shu LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yu CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Pin HU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hsin WEI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L23/00, H01L23/498, H01L25/00, H01L25/065, H01L25/10
CPC Code(s): H01L23/5384
Abstract: a package structure and method for forming the same are provided. the package structure includes a substrate having a front surface and a back surface, and a die formed on the back surface of the substrate. the package structure includes a first through via structure formed in the substrate, a conductive structure formed in a passivation layer) over the front surface of the substrate. the conductive structure includes a via portion in direct contact with the substrate. the package structure includes a connector (formed over the via portion, wherein the connector includes an extending portion directly on a recessed top surface of the via portion.
Inventor(s): Jian-Hong LIN of Yunlin County (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Yen LIU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chun CHANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Li LEE of Yunlin County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ching LEE of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Yih-Ching WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/768, H01L23/522, H01L23/58, H01L27/02
CPC Code(s): H01L23/562
Abstract: an interconnect structure includes a first dielectric layer, a first metal layer, a metal via, and a second metal layer. the first dielectric layer is over a substrate. the first metal layer is over the first dielectric layer and has a first segment and a second segment separated from the first segment. the metal via includes a first portion between the first and second segments of the first metal layer, and a second portion above the first metal layer. the second metal layer is over the metal via. from a top view, the second metal layer includes a metal line extending across the first and second segments of the first metal layer. from a cross-sectional view, the first portion of the metal via has opposite sidewalls respectively offset from opposite sidewalls of the second portion of the metal via.
Inventor(s): Chuei-Tang Wang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Chun Tang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chieh-Yen Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Wei Hsu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/66, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/538, H01Q1/22, H01Q1/24, H01Q13/10
CPC Code(s): H01L23/66
Abstract: an integrated fan-out (info) package includes a die, an encapsulant, and a horn antenna. the die has an active surface and a rear surface opposite to the active surface. the encapsulant laterally encapsulates the die. the horn antenna is electrically connected to the die. the horn antenna includes a top wall and a bottom wall respectively located on two opposite sides of the die and the encapsulant.
Inventor(s): Chuei-Tang Wang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Chun Tang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chieh-Yen Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Wei Hsu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/66, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/538, H01Q1/22, H01Q1/24, H01Q13/10
CPC Code(s): H01L23/66
Abstract: a portion of the top wall is located within a span of the active surface of the die. a portion of the bottom wall is located within a span of the rear surface of the die.
Inventor(s): Chia-Nan Lin of Chiayi (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Cheng Lin of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Horng Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/02
Abstract: a method includes: providing a passivation layer with an embedded mim capacitor; forming a redistribution layer (rdl) above the passivation layer; and forming an opening in the rdl above the mim capacitor, wherein the opening separates the rdl into first and second rdl structures, wherein each of the first and second rdl structures has a convex-shaped profile on a sidewall that defines the opening that separates the first rdl structure from the second rdl structure, and wherein the convex-shaped profile on the sidewalls resists stress migration from the rdl to the mim capacitor to resist stress migration induced cracks forming in the mim capacitor. the forming an opening includes: removing a portion of the rdl to a first depth using first etching operations; and removing a portion of the rdl to a second depth by laterally etching sidewalls of the first and second rdl structures.
Inventor(s): Wei-De HO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Xiang YOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Chien HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szuya LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/522, H01L25/065, H01L25/07, H01L27/088
CPC Code(s): H01L24/08
Abstract: a semiconductor structure includes a first device assembly and a second device assembly. each of the first and second device assembly includes a substrate, a main unit disposed on the substrate and including at least one device, a dielectric unit disposed on the main unit and having an interconnecting surface opposite to the substrate, and an electrically conductive routing disposed in the dielectric unit, electrically connected to the at least one device, and including an end portion. the interconnecting surface of the dielectric unit of the first device assembly is bonded to the interconnecting surface of the dielectric unit of the second device assembly such that the end portion of the electrically conductive routing of the first device assembly is in direct contact with the end portion of the electrically conductive routing of the second device assembly. a method for manufacturing the semiconductor structure are also disclosed.
Inventor(s): Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Sheng Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao Lin of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chen Lai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Shen Yeh of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/31, H01L23/498, H01L25/00
CPC Code(s): H01L24/81
Abstract: a method includes bonding a first package component over a second package component. the second package component includes a plurality of dielectric layers, and a plurality of redistribution lines in the plurality of dielectric layers. the method further includes dispensing a stress absorber on the second package component, curing the stress absorber, and forming an encapsulant on the second package component and the stress absorber.
Inventor(s): Wei-Yu Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hsun Lee of Hsin-chu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L23/00, H01L23/498, H01L23/538
CPC Code(s): H01L25/0657
Abstract: a package structure including a first semiconductor die, at least one second semiconductor die conductive terminals and an insulating encapsulation is provided. the at least one second semiconductor die is stacked on and electrically connected to the first semiconductor die. the conductive terminals are disposed on and electrically connected to the first semiconductor die. the insulating encapsulation laterally encapsulates the first semiconductor die, the at least one second semiconductor die and the conductive terminals, wherein the conductive terminals protrude from a surface of the insulating encapsulation. furthermore, a method for forming the above-mentioned is also provided.
Inventor(s): Shu-Yan Jhu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chiang Ting of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/18, H01L21/56, H01L23/00, H01L23/36, H01L23/48
CPC Code(s): H01L25/18
Abstract: a semiconductor device includes a first semiconductor package comprising: a first interconnect structure on a first semiconductor substrate; through substrate vias electrically coupled to the first interconnect structure extending through the first semiconductor substrate; and a second semiconductor package directly bonded to the first semiconductor package, the second semiconductor package comprising a second semiconductor substrate and a second interconnect structure on the second semiconductor substrate. the semiconductor device further includes a silicon layer on a surface of the second semiconductor package that is opposite to the first semiconductor package; and a heat dissipation structure attached to the silicon layer.
Inventor(s): Yu-Hao Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fong-Yuan Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hsiang Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yi Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jyh Chwen Frank Lee of Palo Alto CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/18, H01L21/48, H01L21/56, H01L23/31, H01L23/367, H01L23/498, H01L23/538
CPC Code(s): H01L25/18
Abstract: a method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.
Inventor(s): Yi-Tse Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ang-Sheng Chou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Li Chiang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Chiang Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Ching Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L23/367, H01L23/522, H01L23/528, H01L29/10, H01L29/24, H01L29/417
CPC Code(s): H01L27/092
Abstract: a semiconductor device includes a gate layer, a channel material layer, a first dielectric layer and source/drain terminals. the gate layer is disposed over a substrate. the channel material layer is disposed over the gate layer, where a material of the channel material layer includes a first low dimensional material. the first dielectric layer is between the gate layer and the channel material layer. the source/drain terminals are in contact with the channel material layer, where the channel material layer is at least partially disposed between the source/drain terminals and over the gate layer, and the gate layer is disposed between the substrate and the source/drain terminals.
Inventor(s): Chih-Fan Huang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Chao Kao of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Yang Hsiao of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Chieh Hsiao of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Ku Shen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Chi Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ming Chen of Hsin-Chu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01G4/005, H01L21/311, H01L21/768, H01L23/522, H10B61/00
CPC Code(s): H01L28/60
Abstract: the present disclosure is directed to a semiconductor device. the semiconductor device includes a multi-layer interconnect structure disposed over a substrate, a dielectric layer disposed over the multi-layer interconnect structure, and a metal-insulator-metal (mim) capacitor disposed over the dielectric layer. the mim capacitor includes a bottom electrode disposed on a top surface of the dielectric layer, a top electrode disposed above the bottom electrode, and an insulating layer interposed between the bottom electrode and the top electrode. the bottom electrode has a slanted sidewall with respect to the top surface of the dielectric layer. the top electrode has a vertical sidewall with respect to the top surface of the dielectric layer. the insulating layer covers the slanted sidewall of the bottom electrode.
Inventor(s): Kuo-Cheng CHING of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei TSAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L27/088, H01L29/417, H01L29/66, H01L29/78
CPC Code(s): H01L29/0649
Abstract: a semiconductor device includes a semiconductor fin, a gate structure, and a dielectric isolation plug. the semiconductor fin extends along a first direction above a substrate and includes a silicon germanium layer and a silicon layer over the silicon germanium layer. the gate structure extends across the semiconductor fin along a second direction perpendicular to the first direction. the dielectric isolation plug extends downwardly from a top surface of the silicon layer into the silicon germanium layer when viewed in a cross section taken along the first direction.
Inventor(s): Chun Hsiung TSAI of Xinpu Township (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hsin KO of Fongshan City (TW) for taiwan semiconductor manufacturing company, ltd., Clement Hsing Jen WANN of Carmel NY (US) for taiwan semiconductor manufacturing company, ltd., Ya-Yun CHENG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/265, H01L21/306, H01L21/3065, H01L29/66
CPC Code(s): H01L29/0653
Abstract: a semiconductor device including a fet includes an isolation insulating layer disposed in a trench of the substrate, a gate dielectric layer disposed over a channel region of the substrate, a gate electrode disposed over the gate dielectric layer, a source and a drain disposed adjacent to the channel region, and an embedded insulating layer disposed below the source, the drain and the gate electrode and both ends of the embedded insulating layer are connected to the isolation insulating layer.
Inventor(s): Yi-Ruei JHAN of Keelung (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Yu WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Ting CHUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Ting PAN of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Shi Ning JU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a method for forming a nanosheet device is provided. the method includes epitaxially growing a conformal semiconductor layer from a first stack of semiconductor layers and a second stack of the semiconductor layers. each of the first and second stack of semiconductor layers includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on each other. a space between the first and second stacks of semiconductor layers is filled with a dielectric fin. the conformal semiconductor layer and the second semiconductor layers may be removed. a metal gate structure is formed over the first semiconductor layers and filling openings created by removal of the conformal semiconductor layer and the second semiconductor layer. a process may be performed on the metal gate structure to form an isolation between the portions of the metal gate structure being separated by a patterning process.
Inventor(s): Shahaji B. MORE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Han LEE of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8234, H01L29/04, H01L29/66, H01L29/78
CPC Code(s): H01L29/41791
Abstract: the present disclosure describes a semiconductor structure and a method for forming the same. the semiconductor structure can include a substrate, a gate structure over the substrate, and a source/drain (s/d) region adjacent to the gate structure. the s/d region can include first and second side surfaces separated from each other. the s/d region can further include top and bottom surfaces between the first and second side surfaces. a first separation between the top and bottom surfaces can be greater than a second separation between the first and second side surfaces.
Inventor(s): Shih-Yao Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Han Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao Wen Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/3065, H01L29/06, H01L29/66, H01L29/78, H01L29/786
CPC Code(s): H01L29/42392
Abstract: a semiconductor device includes a plurality of semiconductor layers vertically separated from one another. each of the plurality of semiconductor layers extends along a first lateral direction. the semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. the lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.
Inventor(s): Hsin-Yi Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Weng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/49, H01L21/02, H01L21/28, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/4908
Abstract: a semiconductor device includes a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions. the gate structure includes: a gate dielectric material around each of the nanosheets; a first liner material around the gate dielectric material; a work function material around the first liner material; a second liner material around the work function material; and a gate electrode material around at least portions of the second liner material.
Inventor(s): Mauricio Manfrini of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yu Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L21/443, H01L29/24, H01L29/45, H01L29/66, H01L29/786, H10B51/30
CPC Code(s): H01L29/78391
Abstract: the present disclosure relates a ferroelectric field-effect transistor (fefet) device. in some embodiments, the fefet device includes a ferroelectric layer having a first side and a second side opposite to the first side and a gate electrode disposed along the first side of the ferroelectric layer. the fefet device further includes an os channel layer disposed along the second side of the ferroelectric layer opposite to the first side and a pair of source/drain regions disposed on opposite sides of the os channel layer. the fefet device further includes a 2d contacting layer disposed along the os channel layer. the os channel layer has a first doping type, and the 2d contacting layer has a second doping type different than the first doping type.
Inventor(s): Jui-Che TSAI of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Lien Linus LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng Hung LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En HUANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H04L9/32, G11C7/06, G11C11/4091, H04L9/08
CPC Code(s): H04L9/3278
Abstract: disclosed is an input/output circuit for a physical unclonable function generator circuit. in one embodiment, a physical unclonable function (puf) generator includes: a puf cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (i/o) circuit each coupled to at least two neighboring columns of the puf cell array, wherein the at least one i/o circuit each comprises a sense amplifier (sa) with no cross-coupled pair of transistors, wherein the sa comprises two cross-coupled inverters with no access transistor and a sa enable transistor, and wherein the at least one i/o circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a puf signature.
Inventor(s): Tetsu OHTOU of HSINCHU CITY (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei TSAI of HSINCHU CITY (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of HSINCHU CITY (TW) for taiwan semiconductor manufacturing company, ltd., Yasutoshi OKUNO of HSINCHU CITY (TW) for taiwan semiconductor manufacturing company, ltd., Jiun-Jia HUANG of YUNLIN COUNTY (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, H01L21/8234, H01L21/8238, H01L27/088, H01L27/092, H01L29/06, H01L29/10
CPC Code(s): H10B10/12
Abstract: a device incudes a substrate. a first fin and a second fin are over the substrate. an isolation structure is laterally between the first fin and the second fin. a gate structure crosses the first fin and the second fin. a first source/drain epitaxy structure is over the first fin. a second source/drain epitaxy structure is over the second fin. a spacer layer extends from a first sidewall of the first fin to a first sidewall of the second fin along a top surface of the isolation structure.
Inventor(s): Hsin-Wen SU of Yunlin County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Kuan LIN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hao LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Lien-Jung HUNG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Wei WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B20/20, H01L21/02, H01L21/306, H01L21/8234, H01L29/06, H01L29/423, H01L29/49, H01L29/66, H01L29/786, H10B20/00
CPC Code(s): H10B20/20
Abstract: a memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. the first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. the first word line is electrically connected to the gate structure of the first transistor. the second word line is electrically connected to the gate structure of the second transistor. the bit line is electrically connected to a first one of the source/drain structures of the first transistor.
Inventor(s): Chao-I Wu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Han-Jong Chia of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/10, H01L21/28, H01L23/522, H01L29/51, H01L29/66, H01L29/78, H10B51/20, H10B51/30
CPC Code(s): H10B51/10
Abstract: provided are a memory device and a method of forming the same. the memory device includes a first tier on a substrate and a second tier on the first tier. the first tier includes a first layer stack; a first gate electrode penetrating through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. the second tier includes a second layer stack; a second gate electrode penetrating through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.
Inventor(s): Han-Jong Chia of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/20, G11C11/22, H10B51/10, H10B51/40
CPC Code(s): H10B51/20
Abstract: a memory device including a word line, memory cells, source lines and bit lines is provided. the memory cells are embedded in and penetrate through the word line. the source lines and the bit lines are electrically connected the memory cells. a method for fabricating a memory device is also provided.
Inventor(s): Hsiang-Ku Shen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ku-Feng Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Wei Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B61/00, G11C11/16, H01L23/522, H01L23/528, H10N50/01, H10N50/10, H10N50/80
CPC Code(s): H10B61/22
Abstract: a semiconductor package includes a first integrated circuit and a second integrated circuit. the first integrated circuit includes a first semiconductor substrate, a first bonding structure bonded to the second integrated circuit, a ferromagnetic layer surrounding the first bonding structure, and a memory cell between the first semiconductor substrate and the first bonding structure.
Inventor(s): Chien-Min Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Yuan Song of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Lin Huang of Menlo Park CA (US) for taiwan semiconductor manufacturing company, ltd., Shy-Jay Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Ying Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Xinyu BAO of Fremont CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B61/00, G11C11/16, G11C11/18, H10N52/00, H10N52/01, H10N52/80
CPC Code(s): H10B61/22
Abstract: provided are a memory device and a method of forming the same. the memory device includes: a selector; a magnetic tunnel junction (mtj) structure, disposed on the selector; a spin orbit torque (sot) layer, disposed between the selector and the mtj structure, wherein the sot layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the mtj structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the sot layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.
Inventor(s): Fu-Ting Sung of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/00, H10B63/00, H10N70/20
CPC Code(s): H10N70/841
Abstract: a memory device, a memory integrated circuit and a manufacturing method of the memory device are provided. the memory device includes a composite bottom electrode, a top electrode and a resistance variable layer disposed between the composite bottom electrode and the top electrode. the composite bottom electrode includes a first bottom electrode and a second bottom electrode disposed over the first bottom electrode. a sidewall of the second bottom electrode is laterally recessed from sidewalls of the first bottom electrode layer and the resistance variable layer.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on June 27th, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- G02B6/12
- G02B6/293
- CPC G02B6/12007
- Taiwan semiconductor manufacturing company, ltd.
- G02B6/124
- G02B6/132
- H01S5/026
- CPC G02B6/12019
- G02B6/30
- G02B6/32
- G02B6/34
- CPC G02B6/30
- G02B6/42
- H01L21/48
- H01L23/498
- CPC G02B6/4202
- H01L23/00
- CPC G02B6/4243
- G03F7/004
- G03F7/09
- H01L21/308
- CPC G03F7/0044
- G03F7/00
- CPC G03F7/70925
- G11C7/06
- G11C5/14
- G11C7/10
- G11C7/14
- CPC G11C7/062
- G11C7/12
- G11C7/18
- G11C8/08
- G11C8/14
- CPC G11C7/1051
- G11C11/16
- H03K19/1776
- CPC G11C11/1673
- G11C11/4094
- G11C11/4074
- G11C11/4096
- G11C11/411
- G11C11/419
- CPC G11C11/4094
- G11C11/418
- G11C11/412
- H03K17/687
- CPC G11C11/418
- CPC G11C11/419
- G11C16/10
- G11C16/26
- H01L29/06
- H01L29/423
- H01L29/78
- CPC G11C16/10
- G11C17/18
- G11C17/16
- CPC G11C17/18
- H01L21/02
- H01L21/768
- CPC H01L21/02068
- H01L21/321
- H01L21/3105
- H01L21/311
- H01L23/522
- CPC H01L21/3212
- H01L21/8234
- H01L21/027
- H01L21/265
- H01L21/324
- H01L21/762
- H01L27/088
- H01L29/08
- H01L29/66
- CPC H01L21/823431
- H01L21/8238
- H01L29/786
- CPC H01L21/823462
- H01L27/092
- CPC H01L21/823807
- H01L23/48
- H01L21/822
- H01L25/065
- CPC H01L23/481
- H01L23/532
- CPC H01L23/53238
- CPC H01L23/53295
- H01L23/538
- H01L25/00
- H01L25/10
- CPC H01L23/5384
- H01L23/58
- H01L27/02
- CPC H01L23/562
- H01L23/66
- H01L21/56
- H01L23/31
- H01Q1/22
- H01Q1/24
- H01Q13/10
- CPC H01L23/66
- CPC H01L24/02
- H01L25/07
- CPC H01L24/08
- CPC H01L24/81
- CPC H01L25/0657
- H01L25/18
- H01L23/36
- CPC H01L25/18
- H01L23/367
- H01L23/528
- H01L29/10
- H01L29/24
- H01L29/417
- CPC H01L27/092
- H01G4/005
- H10B61/00
- CPC H01L28/60
- CPC H01L29/0649
- H01L21/306
- H01L21/3065
- CPC H01L29/0653
- CPC H01L29/0673
- H01L29/04
- CPC H01L29/41791
- CPC H01L29/42392
- H01L29/49
- H01L21/28
- CPC H01L29/4908
- H01L21/443
- H01L29/45
- H10B51/30
- CPC H01L29/78391
- H04L9/32
- G11C11/4091
- H04L9/08
- CPC H04L9/3278
- H10B10/00
- CPC H10B10/12
- H10B20/20
- H10B20/00
- CPC H10B20/20
- H10B51/10
- H01L29/51
- H10B51/20
- CPC H10B51/10
- G11C11/22
- H10B51/40
- CPC H10B51/20
- H10N50/01
- H10N50/10
- H10N50/80
- CPC H10B61/22
- G11C11/18
- H10N52/00
- H10N52/01
- H10N52/80
- H10N70/00
- H10B63/00
- H10N70/20
- CPC H10N70/841
