Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on July 18th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on July 18th, 2024
Taiwan Semiconductor Manufacturing Company, Ltd.: 39 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L29/06 (8), H01L29/66 (8), H01L29/423 (8), H01L29/786 (7), H01L21/8234 (7) H01L23/49822 (2), H01L29/66795 (2), C12M41/38 (1), H01L23/562 (1), H01L24/05 (1)
With keywords such as: layer, structure, semiconductor, gate, source, drain, substrate, memory, dielectric, and disposed in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s): Yi-Hsing Hsiao of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Cheng Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): C12M1/34, C12M1/00, C12M3/00, C12M3/06, C12N5/00, G01N33/50
CPC Code(s): C12M41/38
Abstract: cell monitoring apparatus includes sensing chip and channel module. sensing chip includes channel region, source and drain regions, and sensing film. the channel region includes first semiconductor material. the source and drain regions are disposed at opposite sides of the channel region, and include a second semiconductor material. sensing film is disposed on the channel region at a sensing surface of the sensing chip. channel module is disposed on the sensing surface of sensing chip. a microfluidic channel is formed between the sensing surface of the sensing chip and a proximal surface of the channel module. the microfluidic channel includes a culture chamber and a micro-well. the culture chamber is concave into the proximal surface of the channel module, and overlies the channel region. the micro-well is concave into a side of the culture chamber, and directly faces the sensing film.
Inventor(s): Kuan-Lin Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yi Chou of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Der Sun of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Wei Kang of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): C23C14/35, C23C14/50, H01J37/34
CPC Code(s): C23C14/354
Abstract: a physical vapor deposition (pvd) system includes: a pedestal configured to accommodate a semiconductor wafer; a cover plate above the pedestal configured to hold a target; and a collimator disposed above the pedestal and below the cover plate. the collimator has an upper surface and a lower surface. the lower surface is flat, and the upper surface is non-flat. a first thickness, in a vertical direction, of the collimator at a central portion is smaller than a second thickness, in the vertical direction, of the collimator at a peripheral portion.
Inventor(s): Chih-Neng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Wei Chien of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Chun Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kun-Hsien Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Yuan Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): F24F11/46, G05B13/02
CPC Code(s): F24F11/46
Abstract: a chiller system provides cooling for a semiconductor fabrication facility. the chiller system includes a control system. the control system utilizes one or more analysis models trained with a machine learning process to intelligently assist in reducing the power consumption and enhancing the efficiency of the chiller system.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chuei-Tang Wang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Chia Lin of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Hao Tsai of Huatan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/13, H01L23/00, H01L25/16, H04B10/50
CPC Code(s): G02B6/13
Abstract: an optical interposer is utilized in order to send and receive signals from external sources such as an optical fiber. the optical interposer receives the signals, routes the signals to various attached components, and when desired, converts the signals between optical and electrical signals. the various attached components may include memory devices such as a high bandwidth memory, processing components, such as an xpu, combinations of these, or the like.
Inventor(s): Stefan RUSU of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-wei SONG of Sunnyvale CA (US) for taiwan semiconductor manufacturing company, ltd., Mohammed Rabiul ISLAM of Austin TX (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42, H01L23/367, H01L25/00, H01L25/065, H01L25/18, H01L23/48
CPC Code(s): G02B6/425
Abstract: heterogeneous packaging integration of photonic and electronic elements is described herein. in one embodiment, a disclosed package includes: a package substrate; a first layer comprising an electronic die on the package substrate; and a second layer comprising a photonic die. the second layer is bonded onto the first layer such that the photonic die is bonded onto the electronic die.
Inventor(s): Ming Yang Jung of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chewn-Pu Jou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lan-Chou Cho of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Stefan Rusu of Sunnyvale CA (US) for taiwan semiconductor manufacturing company, ltd., Cheng-Tse Tang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Tai-Chun Huang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., You-Cheng Lu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02F7/00, G02F1/21, G02F1/225, H03M7/00
CPC Code(s): G02F7/00
Abstract: the present disclosure relates to an optical digital-to-analog converter (dac). the optical dac includes a first waveguide path configured to receive a first optical signal and a second waveguide path configured to receive a second optical signal. a first phase shifter segment interfaces with the first and second waveguide paths. the first phase shifter segment is configured to selectively generate a first phase shift between the first optical signal and the second optical signal in response to a first digital input. a second phase shifter segment interfaces with the first and second waveguide paths. the second phase shifter segment is configured to selectively generate a second phase shift between the first optical signal and the second optical signal in response to a second digital input. the first digital input and the second digital input correspond to different bits of a digital signal.
Inventor(s): Lei XU of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., YuKai HOU of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., FangBo GUO of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Bin YUAN of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Jing WANG of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd., Bo LI of Shanghai City (CN) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G05B19/18
CPC Code(s): G05B19/188
Abstract: a method includes using a first pump apparatus to control a pressure condition of a first chamber, wherein the first pump apparatus produces a first operation data in a first digital protocol format; using a second pump apparatus to control a pressure condition of a second chamber, wherein the second pump apparatus produces a second operation data in a second digital protocol format different from the first digital protocol format; receiving, by a box device, the first operation data in the first digital protocol format and the second operation data in the second digital protocol format; decoding, by the box device, the first operation data in the first digital protocol format and the second operation data in the second digital protocol format; determining whether the first operation data is in an acceptable range; and adjusting the first pump apparatus to set the first operation data within the acceptable range.
Inventor(s): Shih-Lien Linus Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/22, H01L29/78, H10B51/30
CPC Code(s): G11C11/2255
Abstract: an efficient fefet-based cam is disclosed which is capable of performing normal read, write but has the ability to match input data with don't-care. more specifically, a ferroelectric fet based ternary content addressable memory is disclosed. the design in some examples utilizes two fefets and four mosfets per cell. the cam can be written in columns through multi-phase writes. it can be used a normal memory with indexing read. it also has the ability for ternary content-based search. the don't-care values can be either the input or the stored data.
Inventor(s): Sanjeev Kumar Jain of Ottawa (CA) for taiwan semiconductor manufacturing company, ltd., Ruchin Jain of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Arun Achyuthan of Stittsville (CA) for taiwan semiconductor manufacturing company, ltd., Atul Katoch of Kanata (CA) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/419, G11C7/10, G11C7/12
CPC Code(s): G11C11/419
Abstract: systems and methods are provided for controlling a wake-up operation of a memory circuit. the memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. a sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. the sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. the memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.
Inventor(s): Shih-Lien Linus Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/56, G11C7/10
CPC Code(s): G11C11/56
Abstract: disclosed herein are related to a memory system and a method of operating the memory system. in one aspect, resistances of a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell are individually set. in one aspect, the first memory cell and the second memory cell are coupled to each other in series between a first line and a second line, and the third memory cell and the fourth memory cell are coupled to each other in series between the second line and a third line. in one aspect, current through the second line according to a parallel resistance of i) a first series resistance of the first memory cell and the second memory cell, and ii) a second series resistance of the third memory cell and the fourth memory cell is sensed. according to the sensed current, multi-level data can be read.
Inventor(s): Hua-Hsin YU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hau-Tai SHIEH of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng Hung LEE of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jen LIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C29/02, G11C29/12, G11C29/14
CPC Code(s): G11C29/026
Abstract: a device is provided and includes a sense amplifier and an output latch circuit. the sense amplifier adjusts voltage levels of first and second data lines according to a bypass data signal corresponding to a data signal in response to a first enable signal having a first logic state and a second enable signal having a second logic state different from the first logic state during a test mode. the output latch circuit generates a data output signal according to the voltage level of the first data line in response to the first enable signal having the second logic state and a third enable signal having the first logic state during the test mode.
Inventor(s): Tsung-Cheng WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsien LIN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Fu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Ying WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01J37/32, H01L21/3205, H01L21/3213, H01L21/67
CPC Code(s): H01J37/32651
Abstract: to reduce the occurrence of current alarms in a semiconductor etching or deposition process, a controller determines an offset in relative positions of a cover ring and a shield over a wafer within a vacuum chamber. the controller provides a position alarm and/or adjusts the position of the cover ring or shield when the offset is greater than a predetermined value or outside a range of acceptable values.
Inventor(s): Hui-Chun LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Hung FENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Peng-Ting LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/033, G03F7/004, G03F7/38
CPC Code(s): H01L21/0337
Abstract: a method of manufacturing a semiconductor device includes the following steps. a photoresist layer is formed over a material layer on a substrate. the photoresist layer is exposed. an organic treatment to the photoresist layer is performed. after performing the organic treatment, the photoresist layer is developed. the material layer is etched using the photoresist layer as a mask.
Inventor(s): Chia-Yun CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kenichi SANO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Wei LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chen LO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/687, B25J15/10, H01J37/20, H01J37/317, H01L21/311, H01L21/3115, H01L21/683
CPC Code(s): H01L21/68785
Abstract: an apparatus includes a supporting frame, a platform supported by the supporting frame and having a first side and a second side opposite to the first side, and at least three robot fingers which are mounted to the supporting frame, and which are angularly displaced from each other. each of the robot fingers has a fingertip configured to retain a substrate on the first side of the platform such that the substrate is spaced apart from the platform. a method for manufacturing a semiconductor structure using the apparatus is also disclosed.
Inventor(s): Hsin-Yi Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Lung Hung of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Da-Yuan Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/027, H01L29/66
CPC Code(s): H01L21/76802
Abstract: a semiconductor device includes a substrate, a first gate structure, and a second gate structure. the first gate structure is disposed on the substrate. the first gate structure includes a first capping layer and a first underlying layer below the first capping layer. the second gate structure is disposed on the substrate. the second gate structure includes a second capping layer and a second underlying layer below the second capping layer. the material of the first capping layer and the second capping layer have a material having higher resistant to oxygen or fluorine than materials of the first underlying layer and the second underlying layer. the first capping layer, the second capping layer and the second underlying layer include a same metal element.
Inventor(s): Sung-Li WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shuen-Shin LIANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Yun PENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Fang-Wei LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hung CHU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Mrunal Abhijith KHADERBAD of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Chu LIN of Pingtung County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/02, H01L21/285, H01L21/306, H01L21/8234, H01L23/522, H01L23/532
CPC Code(s): H01L21/76816
Abstract: a device includes source/drain regions, a gate structure, a source/drain contact, and a tungsten structure. the source/drain regions are over a substrate. the gate structure is between the source/drain regions. the source/drain contact is over one of the source/drain regions. the tungsten structure is over the source/drain contact. the tungsten structure includes a lower portion and an upper portion above the lower portion. the upper portion has opposite sidewalls respectively set back from opposite sidewalls of the lower portion of the tungsten structure.
Inventor(s): Shih-Yao Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuei-Yu Kao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Ping Chen of Toucheng Township (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/02, H01L21/306, H01L21/3065, H01L21/8234, H01L27/088
CPC Code(s): H01L21/76831
Abstract: a method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. the first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. the first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. the method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. the second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.
Inventor(s): Shahaji B. MORE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Wei CHANG of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L27/092
CPC Code(s): H01L21/823814
Abstract: a semiconductor device structure, along with methods of forming such, are described. the method includes forming first and second semiconductor fins in an nmos region and a pmos region, respectively, forming a dielectric feature between the first and second semiconductor fins, recessing the first and second semiconductor fins, forming first and second source/drain epitaxial features over the recessed first and second semiconductor fins, respectively, depositing an interlayer dielectric layer over the first and second source/drain epitaxial features, and forming a first opening in the interlayer dielectric layer to expose a first portion of the first source/drain epitaxial feature and a second opening in the interlayer dielectric layer to expose a first portion of the second source/drain epitaxial feature. the first and second openings are separated by a distance that is about 1.5 times to about 2 times a width of the dielectric feature.
Inventor(s): Chih-Wei Lee of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hung Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Feng Yu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jian-Hao Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsueh-Ju Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Zoe Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/311, H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/786
CPC Code(s): H01L21/823857
Abstract: a semiconductor device includes a first transistor located in a first region of a substrate and a second transistor located in a second region of the substrate. the first transistor includes first channel members vertically stacked above the substrate and a first gate structure wrapping around each of the first channel members. the first gate structure includes a first interfacial layer. the second transistor includes second channel members vertically stacked above the substrate and a second gate structure wrapping around each of the second channel members. the second gate structure includes a second interfacial layer. the second interfacial layer has a first sub-layer and a second sub-layer over the first sub-layer. the first and second sub-layers include different material compositions. a total thickness of the first and second sub-layers is larger than a thickness of the first interfacial layer.
Inventor(s): Hung-Chun Cho of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chih Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Han Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsiang Hu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., HUNG-JUI KUO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L21/48, H01L21/56, H01L23/31
CPC Code(s): H01L23/49822
Abstract: a semiconductor package includes a semiconductor component, a package body, a first rdl structure and an insulation layer. the package body surrounds the semiconductor component and has a first package surface. the first rdl structure is formed on the first package surface of the package body. the insulation layer is formed on the first rdl structure and includes an insulation body, a plurality of recessed portions and a plurality of voids, wherein the insulation body has a first insulation surface, the recessed portions are recessed with respect to the first insulation surface and form a pattern, and the voids are embedded in the insulation body.
Inventor(s): Wen-Shiang Liao of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L23/31, H01L23/58, H01Q1/22, H01Q9/04
CPC Code(s): H01L23/49822
Abstract: a package structure including a first radio frequency die, a second radio frequency die, an insulating encapsulant, a redistribution circuit structure, a first oscillation cavity and a second oscillation cavity is provided. a first frequency range of the first radio frequency die is different from a second frequency range of the second radio frequency die. the insulating encapsulant laterally encapsulates the first radio frequency die and the second radio frequency die. the redistribution circuit structure is disposed on the first radio frequency die, the second die and the insulating encapsulant. the first oscillation cavity is electrically connected to the first radio frequency die, and the second oscillation cavity is electrically connected to the second radio frequency die.
Inventor(s): Guo-Huei WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Zhong ZHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Chun TIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/8234, H01L29/06
CPC Code(s): H01L23/5286
Abstract: a device includes: at a front side of a substrate, a first conductive line; and at a back side of the substrate, first to fifth power rails in a same back side metal layer; and wherein, within a span of a first cell, the second power rail is between the third and fourth power rails; each of the first to fifth power rails is configured different reference voltages first to third reference voltages, the first conductive line is configured to receive a control signal, an input signal, an output signal or one of the reference voltages; and relative to a center of the second power rail, a distribution of the first, second and third reference voltages amongst the first to fifth power rails is (a) symmetric with respect to a first direction and (b) symmetric with respect to perpendicular second direction.
Inventor(s): Shu-Shen YEH of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hua WANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chen LAI of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao LIN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu JENG of Po-Shan Village (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/52, H01L23/053, H01L23/16
CPC Code(s): H01L23/562
Abstract: a semiconductor device package is provided, including a substrate, a semiconductor device, a ring structure, a lid structure, and at least one adhesive member. the semiconductor device is disposed over the substrate. the ring structure is disposed over the substrate and surrounds the semiconductor device. the ring structure comprises a first ring part and a second ring part on opposite sides of the semiconductor device. a first gap is formed between the first ring part and the semiconductor device, a second gap is formed between the second ring part and the semiconductor device, and the first gap is smaller than the second gap. the lid structure is disposed over the ring structure and extends across the semiconductor device. the adhesive member is disposed in the first gap and configured to connect the lid structure and the first surface of the substrate.
Inventor(s): Harry-Haklay Chuang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Wu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Peng Tsai of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/66
CPC Code(s): H01L24/05
Abstract: various embodiments of the present disclosure are directed towards a semiconductor structure (e.g., an integrated circuit (ic) die) comprising an enhanced cap layer for pad oxidation prevention, as well as a method for forming the ic die. an interconnect pad overlies a substrate at a top of an interconnect structure, and a bond structure overlies and extends from a surface of the interconnect pad. a cap layer and an etch stop layer overlie the surface around the bond structure. further, the cap layer separates the etch stop layer from the interconnect pad and is soft. soft may for example, refer to a hardness less than silicon nitride and/or less than the etch stop layer. because the cap layer is soft, a probe may be pushed through the cap layer to the interconnect pad for testing without first forming a pad opening exposing the interconnect pad.
Inventor(s): Tzu-Hsien Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hiroki Noguchi of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hidehiro Fujiwara of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yih Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L25/00
CPC Code(s): H01L25/0657
Abstract: a 3d ic structure includes multiple die layers, such as a top die layer and a bottom die layer. the top die layer and/or the bottom die layer each includes devices such as computing units, analog-to-digital converters, analog circuits, rf circuits, logic circuits, sensors, input/output devices, and/or memory devices. the devices on the first and the second die layers are laterally surrounded by, or adjacent, vertical interconnect structures (vis).
Inventor(s): Wang-Chun HUANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Hou-Yu CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234, H01L29/06, H01L29/423, H01L29/786
CPC Code(s): H01L27/088
Abstract: a device includes a channel layer, a gate structure, a first source/drain structure, a second source/drain structure, and a backside via. the gate structure surrounds the channel layer. the first source/drain structure and the second source/drain structure ate connected to the channel layer. the backside via is connected to a backside of the first source/drain structure. the backside via includes a first portion, a second portion, and a third portion. the first portion is connected to the backside of the first source/drain structure. the third portion tapers from the second portion to the first portion. a sidewall of the third portion is more inclined than a sidewall of the second portion.
Inventor(s): Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L29/423, H01L29/786
CPC Code(s): H01L27/0886
Abstract: a semiconductor device according to the present disclosure includes a first transistor and a second transistor. the first transistor includes first channel members between a first and a second source/drain feature, a first gate structure wrapping around the first channel members, a first source/drain contact disposed over the first source/drain feature, and a first top gate spacer disposed between the first gate structure and the first source/drain contact. the second transistor includes second channel members between a third and a fourth source/drain features, a second gate structure wrapping around the second channel members, a second source/drain contact disposed over the third source/drain feature, and a second top gate spacer disposed between the second gate structure and the second source/drain contact. a distance between the second gate spacer and the second source/drain contact is greater than a distance between the first gate spacer and the first source/drain contact.
Inventor(s): Chien Yao Huang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ti Su of Tainan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/761, H01L21/8238, H01L29/10, H01L21/74, H01L29/78
CPC Code(s): H01L27/0921
Abstract: the present disclosure describes a metal-oxide-semiconductor field-effect transistor (mosfet) device. the mosfet device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. the second-type well and the deep-second-type well form an enclosed space that includes the first-type well. the mosfet also includes an embedded semiconductor region (esr) in a vicinity of the enclosed space. the esr includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.
Inventor(s): Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/118
CPC Code(s): H01L27/11807
Abstract: a method for manufacturing a semiconductor structure includes defining active areas extending in an x-direction, arranged in a y-direction, and on a substrate. each of the active areas has nanostructures. the method further includes forming dummy gate structures across the active areas in the y-direction, forming merged source/drain features in the active areas and on opposite sides of the dummy gate structures in the x-direction, forming dielectric structures in the active areas to cut each of the merged source/drain features into a first source/drain feature and a second source/drain feature, and to cut each of the dummy gate structures into segments, and replacing the segments of the dummy gate structures with gate structures wrapping around the nanostructures in the active areas. the dielectric structures are in contact with sidewalls of the first source/drain features, the second source/drain features, and the gate structures.
Inventor(s): Tsung Hsien Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Yu Chou of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-En Chen of () for taiwan semiconductor manufacturing company, ltd., Shyh-Fann Ting of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/1464
Abstract: a process of forming a back side deep trench isolation structure for an image sensing device includes etching first trenches in the back side of a semiconductor substrate, lining the first trenches with dielectric, depositing passivation layers over and within the first trenches, and etching second trenches through the passivation layers into the first trenches, and filling the second trenches to form a substrate-embedded metal grid. optionally, the bottoms of the first trenches are filled by depositing and etching a lower fill material prior to depositing the passivation layers. the method prevents the passivation layers from pinching off in a way that causes voids within the first trenches. the result is better optical performance such as increased quantum efficiency and reduced crosstalk.
Inventor(s): Hsin-Cheng LIN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tao CHOU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chee-Wee LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522
CPC Code(s): H01L28/91
Abstract: a method includes forming a sacrificial multi-layer stack including first, second, and third sacrificial layers stacked in a vertical direction on a substrate; removing the first sacrificial layer to form a first space; depositing a first dielectric layer and a first electrode material in the first space; removing the second sacrificial layer to form a second space; depositing a second dielectric layer and a second electrode material in the second space; removing the third sacrificial layer to form a third space; depositing a third dielectric layer and a third electrode material in the third space.
Inventor(s): Kuei-Ming Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Ming Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Yi Yu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L21/02, H01L21/84, H01L27/088, H01L27/12, H01L29/167, H01L29/417, H01L29/66
CPC Code(s): H01L29/0847
Abstract: various embodiments of the present disclosure are directed towards an integrated chip including a first transistor on a semiconductor substrate. the first transistor includes a first gate structure over the semiconductor substrate, a first pair of source/drain regions on opposing sides of the first gate structure, and a pair of diffusion barrier structures between the first pair of source/drain regions and a lower region of the semiconductor substrate. the first pair of source/drain regions comprise a first dopant. the diffusion barrier structures are co-doped with the first dopant and a second dopant different from the first dopant. a doping concentration of the first dopant within the first pair of source/drain regions is greater than a doping concentration of the first dopant within the diffusion barrier structures.
Inventor(s): Lung-Kun Chu of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Mao-Lin Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Wei Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jia-Ni Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/02, H01L21/306, H01L21/311, H01L21/768, H01L23/528, H01L29/06, H01L29/423, H01L29/45, H01L29/66, H01L29/786
CPC Code(s): H01L29/41733
Abstract: a semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. the backside source contact extends through the bottom dielectric layer.
Inventor(s): Cheng-Yi PENG of Taipei City 112 (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Song-Bor LEE of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H01L29/66439
Abstract: the structure of a semiconductor device with passivation layers on active regions of fet devices and a method of fabricating the semiconductor device are disclosed. the semiconductor device includes a substrate, first and second source/drain (s/d) regions disposed on the substrate, nanostructured channel regions disposed between the first and second s/d regions, a passivation layer, and a nanosheet (ns) structure wrapped around the nanostructured channel regions. each of the s/d regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers. a first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalls of the nanostructured channel regions
Inventor(s): Chun-Fu LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lung-Kun CHU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jia-Ni YU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Mao-Lin HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Wei HSU of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/285, H01L21/306, H01L29/06, H01L29/423, H01L29/786
CPC Code(s): H01L29/66545
Abstract: a method for forming a semiconductor device structure includes forming nanostructures in a first region and a second region over a substrate. the method also includes forming a gate dielectric layer surrounding the nanostructures. the method also includes forming dummy structures between the nanostructures. the method also includes forming a dielectric layer over the nanostructures. the method also includes forming a dielectric structure between the nanostructures in the first region and nanostructures in the second region. the method also includes removing the dummy structures in the first region. the method also includes depositing a first work function layer over the nanostructures. the method also includes removing the first work function layer and the dummy structures in the second region. the method also includes depositing a second work function layer over the nanostructures.
Inventor(s): Shahaji B. MORE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chun Hsiung TSAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/8234, H01L29/06, H01L29/423, H01L29/78, H01L29/786, H01L21/762
CPC Code(s): H01L29/66795
Abstract: the present disclosure is directed to methods for the fabrication of gate-all-around (gaa) field effect transistors (fets) with low power consumption. the method includes depositing a first and a second epitaxial layer on a substrate and etching trench openings in the first and second epitaxial layers and the substrate. the method further includes removing, through the trench openings, portions of the first epitaxial layer to form a gap between the second epitaxial layer and the substrate and depositing, through the trench openings, a first dielectric to fill the gap and form an isolation structure. in addition, the method includes depositing a second dielectric in the trench openings to form trench isolation structures and forming a transistor structure on the second epitaxial layer.
Inventor(s): Ru-Shang Hsiao of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hwanq Su of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Pin Chia Su of Tainan County (TW) for taiwan semiconductor manufacturing company, ltd., Ying Hsin Lu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., I-Shan Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L29/78
CPC Code(s): H01L29/66795
Abstract: a method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. a semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.
Inventor(s): Ming-Heng TSAI of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Sheng LIANG of Changhua (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., JHON JHY LIAW of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/775, H01L29/06, H01L29/08, H01L29/423, H01L29/66
CPC Code(s): H01L29/775
Abstract: a semiconductor device structure includes a dielectric wall disposed over a substrate, a plurality of first semiconductor layers vertically stacked and extended outwardly from a first side of the dielectric wall, a plurality of second semiconductor layers vertically stacked and extended outwardly from a second side of the dielectric wall, a first epitaxial source/drain (s/d) feature disposed on the first side of the dielectric wall, a second epitaxial s/d feature disposed on the second side of the dielectric wall, a first bottom dielectric layer extended outwardly from the first side of the dielectric wall, and a second bottom dielectric layer extended outwardly from the second side of the dielectric wall.
Inventor(s): Yuan-Tai Tseng of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B63/00, H10N70/00, H10N70/20
CPC Code(s): H10B63/84
Abstract: the present disclosure relates to an integrated chip including a first word line and a second word line adjacent to the first word line. the first word line and the second word line both extend along a first direction. a first memory cell is over the first word line and a second memory cell is over the second word line. a first bit line extends over the first memory cell, over the second memory cell, and along a second direction transverse to the first direction. a first dielectric layer is arranged between the first memory cell and the second memory cell. the first dielectric layer extends in a first closed loop to form and enclose a first void within the first dielectric layer. the first void laterally separates the first memory cell from the second memory cell.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on July 18th, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- C12M1/34
- C12M1/00
- C12M3/00
- C12M3/06
- C12N5/00
- G01N33/50
- CPC C12M41/38
- Taiwan semiconductor manufacturing company, ltd.
- C23C14/35
- C23C14/50
- H01J37/34
- CPC C23C14/354
- F24F11/46
- G05B13/02
- CPC F24F11/46
- G02B6/13
- H01L23/00
- H01L25/16
- H04B10/50
- CPC G02B6/13
- G02B6/42
- H01L23/367
- H01L25/00
- H01L25/065
- H01L25/18
- H01L23/48
- CPC G02B6/425
- G02F7/00
- G02F1/21
- G02F1/225
- H03M7/00
- CPC G02F7/00
- G05B19/18
- CPC G05B19/188
- G11C11/22
- H01L29/78
- H10B51/30
- CPC G11C11/2255
- G11C11/419
- G11C7/10
- G11C7/12
- CPC G11C11/419
- G11C11/56
- CPC G11C11/56
- G11C29/02
- G11C29/12
- G11C29/14
- CPC G11C29/026
- H01J37/32
- H01L21/3205
- H01L21/3213
- H01L21/67
- CPC H01J37/32651
- H01L21/033
- G03F7/004
- G03F7/38
- CPC H01L21/0337
- H01L21/687
- B25J15/10
- H01J37/20
- H01J37/317
- H01L21/311
- H01L21/3115
- H01L21/683
- CPC H01L21/68785
- H01L21/768
- H01L21/027
- H01L29/66
- CPC H01L21/76802
- H01L21/02
- H01L21/285
- H01L21/306
- H01L21/8234
- H01L23/522
- H01L23/532
- CPC H01L21/76816
- H01L21/3065
- H01L27/088
- CPC H01L21/76831
- H01L21/8238
- H01L27/092
- CPC H01L21/823814
- H01L29/06
- H01L29/423
- H01L29/786
- CPC H01L21/823857
- H01L23/498
- H01L21/48
- H01L21/56
- H01L23/31
- CPC H01L23/49822
- H01L23/58
- H01Q1/22
- H01Q9/04
- H01L23/528
- CPC H01L23/5286
- H01L21/52
- H01L23/053
- H01L23/16
- CPC H01L23/562
- H01L21/66
- CPC H01L24/05
- CPC H01L25/0657
- CPC H01L27/088
- CPC H01L27/0886
- H01L21/761
- H01L29/10
- H01L21/74
- CPC H01L27/0921
- H01L27/118
- CPC H01L27/11807
- H01L27/146
- CPC H01L27/1464
- CPC H01L28/91
- H01L29/08
- H01L21/84
- H01L27/12
- H01L29/167
- H01L29/417
- CPC H01L29/0847
- H01L29/45
- CPC H01L29/41733
- H01L29/775
- CPC H01L29/66439
- CPC H01L29/66545
- H01L21/762
- CPC H01L29/66795
- CPC H01L29/775
- H10B63/00
- H10N70/00
- H10N70/20
- CPC H10B63/84
