Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on August 8th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on August 8th, 2024
Taiwan Semiconductor Manufacturing Company, Ltd.: 71 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L29/66 (19), H01L29/06 (17), H01L23/00 (12), H01L21/8234 (12), H01L21/02 (11) H01L29/0673 (3), H01L23/5389 (2), H01L25/105 (2), H01L25/50 (2), H01L23/5226 (2)
With keywords such as: layer, structure, semiconductor, dielectric, gate, forming, substrate, fin, region, and metal in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s): Yu-Ting Chiu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Jui Huang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Ling Hwang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B32B37/18
CPC Code(s): B32B37/18
Abstract: a method for laminating a film to a wafer and apparatus for performing the lamination process are disclosed. the method includes providing the wafer and the film in a process chamber where the wafer and the film are separated from each other, achieving a vacuum state and a process temperature in the process chamber, and laminating the film to contact a surface of the wafer.
Inventor(s): Yang-Che CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Victor Chiang LIANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua LIN of Douliu City (TW) for taiwan semiconductor manufacturing company, ltd., Chwen-Ming LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Wen TSENG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chuan TENG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B81B7/04, B81C1/00, B81C3/00
CPC Code(s): B81B7/04
Abstract: a micro electro mechanical system (mems) includes a circuit substrate, a first mems structure disposed over the circuit substrate, and a second mems structure disposed over the first mems structure.
Inventor(s): Chih-Tsung Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hau-Yan Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Kang Liu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yingkit Felix Tsui of Cupertino CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/12, G02B6/13
CPC Code(s): G02B6/12004
Abstract: various embodiments of the present disclosure are directed towards a semiconductor package comprising optically coupled integrated circuit (ic) chips. a first ic chip and a second ic chip overlie a substrate at a center of the substrate. a photonic chip overlies the first and second ic chips and is electrically coupled to the second ic chip. a laser device chip overlies the substrate, adjacent to the photonic chip and the second ic chip, at a periphery of the substrate. the photonic chip is configured to modulate a laser beam from the laser device chip in accordance with an electrical signal from the second ic chip and to provide the modulated laser beam to the first ic chip. this facilitates optical communication between the first ic chip to the second ic chip. various embodiments of the present disclosure are further directed towards simultaneously aligning and bonding constituents of the semiconductor package.
Inventor(s): Shih Wei Liang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Chou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Nien-Fang Wu of Chiayi City (TW) for taiwan semiconductor manufacturing company, ltd., Jiun Yi Wu of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42, H01L25/16
CPC Code(s): G02B6/4214
Abstract: package devices and methods of manufacture are discussed. in an embodiment, a method of manufacturing an integrated circuit device includes: forming an optical device layer; forming an optical layer on the optical device layer; after the forming the optical layer, forming a first opening in the optical layer; and embedding a reflective structure in the first opening.
Inventor(s): Pei-Cheng Hsu of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Fu Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Cheng Lien of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chang Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/24, G03F1/70, G03F7/20
CPC Code(s): G03F1/24
Abstract: the present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (euvl). the method includes receiving an euvl mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. the method further includes patterning the absorber layer to form a trench on the euvl mask, wherein the trench has a first width above a target width. the method further includes treating the euvl mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. the method may also include treating the euvl mask with nitrogen plasma to protect the capping layer, wherein the treating of the euvl mask with the nitrogen plasma expands the trench to a third width at the target width.
Inventor(s): An-Ren ZI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hsiang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yuansun Village (TW) for taiwan semiconductor manufacturing company, ltd., Yahru CHENG of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/004, G03F7/038, G03F7/32, H01L21/027, H01L21/47
CPC Code(s): G03F7/0048
Abstract: a photoresist developer includes a solvent having hansen solubility parameters of 15<�<25, 10<�<25, and 6<�<30; an acid having an acid dissociation constant, pka, of −15<pka<4, or a base having a pka of 40>pka>9.5; and a chelate.
Inventor(s): Ya Tung HAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huang-YU CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/3323, G06N3/08
CPC Code(s): G06F30/3323
Abstract: a method includes constructing a set of reference design contents associated with a set of reference design recipes. the method also includes determining a content similarity between a user design content and a reference design content taken from the set of reference design contents. the method further includes executing a design flow specified by a reference design recipe associated with the reference design content, as a result of the content similarity reaching a predetermined threshold.
Inventor(s): Hsin-Wen SU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kian-Long LIM of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chun KENG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Ta YANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hao LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C17/18, G11C7/18, H10B20/00
CPC Code(s): G11C17/18
Abstract: a semiconductor memory device includes a first word line formed over a first active region. in some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. in some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.
Inventor(s): Cheng-Ming Lin of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Hua Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kenichi Sano of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yen Woon of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, C23C16/40, C23C16/56, H01L21/3105
CPC Code(s): H01L21/02337
Abstract: a low thermal budget dielectric material treatment is provided. an example method of the present disclosure includes providing a semiconductor structure, depositing a dielectric material over the semiconductor structure, treating the dielectric material with a gaseous species carried in a supercritical fluid, and after the treating, reducing a thickness of the dielectric material.
Inventor(s): Hsin-Che Chiang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chih Kao of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Sheng Liang of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Hua Pan of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, H01L29/08, H01L29/66, H01L29/78
CPC Code(s): H01L21/0245
Abstract: a semiconductor device includes a semiconductor substrate having a first lattice constant, a fin-shape base protruding from the semiconductor substrate and extending lengthwise in a first direction, nanostructures suspended above the fin-shape base, a metal gate structure wrapping around each of the nanostructures, an epitaxial feature abutting the nanostructures, and inner spacers interposing the epitaxial feature and the metal gate structure. in a cross section perpendicular to the first direction the fin-shape base includes a first layer and a second layer over the first layer. the first layer has a second lattice constant different from the first lattice constant, and the second layer has a third lattice constant different from the second lattice constant. a portion of the metal gate structure is sandwiched between the second layer and a bottommost one of the nanostructures.
Inventor(s): Ming-Hsun LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Jung CHEN of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu JIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/3065, H01J37/32, H01L21/683
CPC Code(s): H01L21/3065
Abstract: some implementations described herein include an etch tool including a combination bottom shadow ring component including a moveable inner ring component and a fixed inner ring component. the moveable inner ring component provides for an adjustability of an effective thickness of the combination bottom shadow ring component during an etching operation. the adjustability (e.g., “tunability”) of the effective thickness of the combination bottom shadow ring component enables flexibility and is conducive to changes in one or more parameters related to different etch recipes for a semiconductor substrate. additionally, the fixed inner ring component shadows beveled regions of the semiconductor substrate during the etching operation to reduce a likelihood of damage to the beveled regions.
Inventor(s): Wen-Hsiung LU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Da CHENG of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Su-Fei LIN of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Hsu-Lun LIU of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Pin CHAN of Pingzhen City (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Sheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/48, C25D5/00, H01L23/00, H01L23/498, H01L23/538
CPC Code(s): H01L21/4853
Abstract: in a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. a first photoresist layer is formed over the first conductive layers. the first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. a connection pattern is formed to connect the island pattern and the bus bar pattern. a second photoresist layer is formed over the first conductive layers and the connection pattern. the second photoresist layer includes an opening over the island pattern. second conductive layers are formed on the island pattern in the opening. the second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.
Inventor(s): Lee-Chuan Tseng of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, B65G47/90, G01V8/12
CPC Code(s): H01L21/67265
Abstract: a method includes generating a first beam of radiation toward a first slot of a workpiece carrier. the first beam of radiation has a first beam area that is greater than or equal to an area of an opening of the first slot. the method further includes measuring a reflected portion of the first beam of radiation that is reflected toward, and impinges on, a radiation sensor. the method further includes determining if the first slot of the workpiece carrier is holding a workpiece based on the measured reflected portion of the first beam of radiation.
Inventor(s): Chih-Han LIN of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Kuei-Yu KAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Yao LIN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ke-Chia TSENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Min Chiao LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Chung HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hung CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Guan Kai HUANG of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Cheng CHEN of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Ping CHEN of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Ching CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/762, H01L21/8238, H01L27/088
CPC Code(s): H01L21/76224
Abstract: a semiconductor device includes a fin extending from a substrate and including a first fin end, a separation structure separating the first fin end from an adjacent fin end of another fin, a dummy gate spacer along sidewalls of the separation structure and the fin, a first epitaxial source/drain region in the fin and adjacent the separation structure, and a residue of a dummy gate material in a corner region between the dummy gate spacer and the first fin end. the first fin end protrudes from the dummy gate spacer into the separation structure. the residue of the dummy gate material separates the first epitaxial source/drain region from the separation structure and is triangle shaped.
Inventor(s): Hsin-Yen HUANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Ching CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/02, H01L21/306, H01L21/311
CPC Code(s): H01L21/76816
Abstract: integrated circuit devices and methods of forming the same are provided. a method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ild layer over the semiconductor substrate, and a first metal feature in the first ild layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ild layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ild layer; and depositing a second ild layer over the workpiece.
Inventor(s): Wei-Hao LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsi-Wen TIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Teng DAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chieh YAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hwei-Jay CHU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, C08F10/02, C08F10/06, C08F20/06, C08F20/32, H01L21/311, H01L23/532
CPC Code(s): H01L21/7682
Abstract: a method for manufacturing a semiconductor device includes: forming metal lines on a conductive interconnect structure disposed on a substrate; forming functionalized polymers, each of which includes a carbon-based polymer chain and a functional group that is bonded to a lateral surface of a corresponding one of the metal lines and that is represented by formula (a):
Inventor(s): Wei-Hao LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsi-Wen TIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Teng DAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chieh YAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hwei-Jay CHU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, C08F10/02, C08F10/06, C08F20/06, C08F20/32, H01L21/311, H01L23/532
CPC Code(s): H01L21/7682
Abstract:
Inventor(s): Wei-Hao LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsi-Wen TIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Teng DAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chieh YAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hwei-Jay CHU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, C08F10/02, C08F10/06, C08F20/06, C08F20/32, H01L21/311, H01L23/532
CPC Code(s): H01L21/7682
Abstract: wherein r1, r2, r3 are defined herein; removing the carbon-based polymer chain of an upper portion of the functionalized polymers to leave the carbon-based polymer chain of remainder of the functionalized polymers and to form recesses; forming a dielectric layer to fill the recesses; and removing the carbon-based polymer chain of the remainder of the functionalized polymers to form air gaps among the metal lines.
Inventor(s): Hao Yang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Hsun Wu of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Neng-Jye Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jye-Yen Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522
CPC Code(s): H01L21/76883
Abstract: devices with metal structures formed with seams and methods of fabrication are provided. an exemplary method includes forming a metal plug having a top surface formed with a seam; depositing a film over the top surface of the metal plug and at least partially filling the seam; and etching the film from over the metal plug, wherein the film remains in the seam.
Inventor(s): Te-Chih HSIUNG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Peng WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jyun-De WU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Just LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/311, H01L29/66
CPC Code(s): H01L21/76897
Abstract: a semiconductor structure includes a semiconductive fin, a gate structure, a plurality of source/drain regions, an un-oxidized dielectric cap, and an oxidized dielectric cap. the gate structure extends across the semiconductive fin. the source/drain regions are over the semiconductive fin and at opposite sides of the gate structure. the un-oxidized dielectric cap is atop the gate structure. the oxidized dielectric cap is atop the oxidized dielectric cap.
Inventor(s): Min-Feng Kao of Chiayi City (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Chih Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/48
CPC Code(s): H01L21/76898
Abstract: methods and devices of having an enclosure structure formed in a multi-layer interconnect and a through-silicon-via (tsv) extending through the enclosure structure. in some implementations, a protection layer is formed between the enclosure structure and the tsv.
Inventor(s): Huan-Chieh Su of Tianzhong Township (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Zhi-Chang Lin of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Zhen Yu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L29/66, H01L29/78
CPC Code(s): H01L21/823431
Abstract: a method of forming a semiconductor transistor device. the method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. the method further comprises forming a gate structure surrounding the fin structure. the method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. the method further comprises forming a back-side dielectric cap in the back-side capping trench.
Inventor(s): Ta-Chun Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Hua Pan of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yung Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L29/66
CPC Code(s): H01L21/823431
Abstract: a method of forming a semiconductor structure includes forming a semiconductor fin over a substrate, forming a dummy gate stack over the semiconductor fin, depositing a dielectric layer over the dummy gate stack, and selectively etching the dielectric layer, such that a top portion and a bottom portion of the dielectric layer form a step profile. the method further includes removing portions of the dielectric layer to form a gate spacer and subsequently forming a source/drain feature in the semiconductor fin adjacent to the gate spacer.
Inventor(s): Tzu-Ging LIN of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chang HUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shun- Hui YANG of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/762, H01L27/088
CPC Code(s): H01L21/823481
Abstract: in a method of manufacturing a semiconductor device, a fin structure is formed. the fin structure includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure, and a hard mask layer over the stacked layer. an isolation insulating layer is formed so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer. a sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. a first dielectric layer is formed, and a second dielectric layer made of a different material than the first dielectric layer is formed over the first dielectric layer. the second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer, thereby forming a wall fin structure.
Inventor(s): Shih-Yao Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Han Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Ping Chen of Toucheng Township (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao Wen Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, B82Y10/00, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L21/823481
Abstract: a method for making a semiconductor device includes: forming a first through sixth fin structures over a substrate, all extending along a first lateral direction, the second fin structure separated from each of the first and third fin structures with a first distance, the fifth fin structure separated from each of the fourth and sixth fin structures with the first distance, and the third fin structure separated from the fourth fin structure with a second distance; forming gate structures overlaying a respective portion of each of the first through sixth fin structures; forming a first through sixth pairs of trenches by removing respective portions of each of the first through sixth fin structures not overlaid by the gate structures; forming a dielectric passivation layer over the third and fourth pairs of trenches; and growing source/drain structures in the first, second, fifth, and sixth pairs of trenches, respectively.
Inventor(s): Wei-Liang Lu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Yin Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jian-Hsuan Zheng of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Che-Cheng Chang of Cupertino CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L27/092, H01L29/10, H01L29/66
CPC Code(s): H01L21/823821
Abstract: a method of fabricating a semiconductor structure includes forming a semiconductor fin over a substrate. the method includes forming a semiconductor fin over a substrate. the method includes forming an isolation region around the semiconductor fin. the method includes forming a dummy gate structure over the semiconductor fin, which further includes performing a first etching process using a first etchant and subsequently performing a second etching process using a second etchant, where the first etchant is different from the second etchant in composition. the method includes forming source/drain features adjacent the dummy gate structure. the method includes replacing the dummy gate structure with a metal gate structure that is interposed between the source/drain features.
Inventor(s): Chien-Yuan Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Ping Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Ming Lee of Yangmei City (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Kai Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Mei-Yun Wang of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/033, H01L21/311, H01L27/092
CPC Code(s): H01L21/823821
Abstract: an embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ild) layer on the fins; forming masking layers on the ild layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ild layer using the patterned masking layers as an etching mask.
Inventor(s): Szu-Ying Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Kang Ho of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Sen-Hong Syue of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Huicheng Chang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/02, H01L21/311, H01L21/762, H01L27/092
CPC Code(s): H01L21/823878
Abstract: a device includes a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a dielectric fin over the substrate, a first isolation region between the first semiconductor fin and the dielectric fin, and a second isolation region between the first semiconductor fin and the second semiconductor fin. the first semiconductor fin is disposed between the second semiconductor fin and the dielectric fin. the first isolation region has a first concentration of an impurity. the second isolation region has a second concentration of the impurity. the second concentration is less than the first concentration. a top surface of the second isolation region is disposed closer to the substrate than a top surface of the first isolation region.
Inventor(s): Pei-Hsuan LEE of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Ming CHEN of Taiwan (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Shing CHEN of Taiwan (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsiang CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Xiaomeng CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, G01N23/2251, H01L21/02
CPC Code(s): H01L22/12
Abstract: a high atomic number material is applied to one or more surfaces of a semiconductor structure of a wafer. the one or more surfaces are at a depth different from a depth of a surface of the wafer. an electron beam is scanned over the semiconductor structure to cause a backscattered electron signal to be collected at a collector. a profile scan of the semiconductor structure is generated based on an intensity of the backscattered electron signal, at the collector, resulting from the high atomic number material. the high atomic number material increases the intensity of the backscattered electron signal for the one or more surfaces of the semiconductor structure such that contrast in the profile scan is increased. the increased contrast of the profile scan enables accurate critical dimension measurements of the semiconductor structure.
Inventor(s): Chih-Hao Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yuan Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pu Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Hui Cheng of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Wei Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L21/48, H01L21/56, H01L21/683, H01L21/78, H01L23/00, H01L23/29, H01L23/31, H01L23/538, H01L25/00, H01L25/065
CPC Code(s): H01L23/3675
Abstract: a manufacturing method of a package structure includes: forming a first package component over a temporary carrier, wherein the first package component comprises a semiconductor die encapsulated by an insulating encapsulation material that comprises a base layer and a plurality of fillers inside the base layer; de-bonding the temporary carrier to expose a rear side of the semiconductor die, wherein during the de-bonding, a portion of the fillers is accessibly revealed from the base layer to form an insulating encapsulation; forming a metallic layer on the rear side of the semiconductor die and the portion of the fillers of the insulating encapsulation; and coupling a heat dissipating component to the first package component at least through the metallic layer.
Inventor(s): Jaw-Juinn HORNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Lin LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Lin LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L23/00
CPC Code(s): H01L23/3677
Abstract: an ic device includes a heat transfer structure electrically isolated from a resistor. the resistor includes first and second metal segments extending in a first direction in a first metal layer and a third metal segment extending perpendicular to the first direction in a second metal layer below the first metal layer, the third metal segment electrically connecting the first and second metal segments to each other. the heat transfer structure includes fourth and fifth metal segments extending in the first direction in the first metal layer adjacent to the first and second metal segments, sixth and seventh metal segments extending in the second direction in the second metal layer, each of the sixth and seventh metal segments electrically connecting the fourth and fifth metal segments to each other, and a thermally conductive path extending from the sixth or seventh metal segment to an underlying active area.
Inventor(s): Cai-Ling WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Wen HSUEH of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., An-Jiao FU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chii-Ping CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Hung WANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528, H01L23/532
CPC Code(s): H01L23/5226
Abstract: a method for manufacturing a semiconductor structure is provided. the semiconductor structure includes an aluminum-containing layer and an etch stop layer formed over the aluminum-containing layer. the semiconductor structure further includes a carbon-containing dielectric layer formed over the etch stop layer. the semiconductor structure further includes a metal line formed in an upper portion of the carbon-containing dielectric layer. the semiconductor structure further includes a conductive via formed in a lower portion of the carbon-containing dielectric layer and through the etch stop layer and the aluminum-containing layer. the semiconductor structure further includes a barrier layer interposing the first sidewall of the metal line and carbon-containing dielectric layer and interposing the second sidewall of the conductive via and the carbon-containing dielectric layer.
Inventor(s): Jhon-Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/311, H01L21/768, H01L23/532, H01L27/092
CPC Code(s): H01L23/5226
Abstract: a device includes semiconductor channel region, source/drain regions, a source/drain contact, a first dielectric layer, a second dielectric layer, and a tungsten via. the source/drain regions are at opposite sides of the semiconductor channel region. the source/drain contact is over one of the source/drain regions. the first dielectric layer is over the source/drain contact. the second dielectric layer is over the first dielectric layer. the tungsten via extends through the first and second dielectric layers to the source/drain contact. the tungsten via includes a first portion over the source/drain contact and a second portion over the first portion. the second portion includes a tungsten sidewall laterally offset from a tungsten sidewall of the first portion, and a tungsten surface interfacing a top surface of the first dielectric layer.
Inventor(s): Chen-Fong Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-I Chu of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Jyh-Cherng Sheu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huicheng Chang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L23/367, H01L23/46, H01L29/06, H01L29/40, H01L29/417, H01L29/423
CPC Code(s): H01L23/528
Abstract: semiconductor devices having improved heat dissipation and methods of forming the same are disclosed. in an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including front-side conductive lines; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including backside conductive lines, the backside conductive lines having line widths greater than line widths of the front-side conductive lines; and a first heat dissipation substrate coupled to the backside interconnect structure.
Inventor(s): Joung-Wei Liou of Zhudong Town (TW) for taiwan semiconductor manufacturing company, ltd., Chin Kun Lan of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/02, H01L21/768
CPC Code(s): H01L23/5329
Abstract: the present disclosure relates to a method of forming a semiconductor structure. the method includes depositing an etch-stop layer (esl) over a first dielectric layer. the esl layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the first precursor; flowing a second precursor over the first dielectric layer to form a sublayer of the esl layer; and purging at least a portion of the second precursor. the method can further include depositing a second dielectric layer on the esl layer and forming a via in the second dielectric layer and through the esl layer.
Inventor(s): Feng Wei Kuo of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chewn-Pu Jou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shuo-Mao Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, G02B6/42, H01L21/48, H01L21/56, H01L21/683, H01L23/00, H01L23/31, H01L23/498, H01L25/00, H01L25/18
CPC Code(s): H01L23/5386
Abstract: an integrated circuit package integrates a photonic die (odie) and an electronic die (edie). more specifically, the integrated circuit package may include a plurality of redistribution layers communicatively coupled to at least one of the odie and/or the edie, where molded material at least partially surrounds the at least one of the odie and/or the edie.
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L21/683, H01L21/78, H01L23/00, H01L23/31, H01L25/00, H01L25/10
CPC Code(s): H01L23/5389
Abstract: a package includes a redistribution structure, a die package on a first side of the redistribution structure including a first die connected to a second die by metal-to-metal bonding and dielectric-to-dielectric bonding, a dielectric material over the first die and the second die and surrounding the first die, and a first through via extending through the dielectric material and connected to the first die and a first via of the redistribution structure, a semiconductor device on the first side of the redistribution structure includes a conductive connector, wherein a second via of the redistribution structure contacts the conductive connector of the semiconductor device, a first molding material on the redistribution structure and surrounding the die package and the semiconductor device, and a package through via extending through the first molding material to contact a third via of the redistribution structure.
Inventor(s): Yan-Fu Lin of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Tsan Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L23/00, H01L23/31, H01L23/528, H01L25/10
CPC Code(s): H01L23/5389
Abstract: a fan-out package having a main die and a dummy die side-by-side is provided. a molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.
Inventor(s): Shang-Yun Hou of Jubei (TW) for taiwan semiconductor manufacturing company, ltd., Weiming Chris Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chiang Ting of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Pin Hu of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chih Chiou of Zhunan Township (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L21/683, H01L23/31, H01L23/538, H01L25/00, H01L25/065
CPC Code(s): H01L23/562
Abstract: embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. the interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.
Inventor(s): Hao Chun Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wen Hsiao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ching Hsu of Chung-Ho City (TW) for taiwan semiconductor manufacturing company, ltd., Mirng-Ji Lii of Sinpu Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/56, H01L21/78, H01L23/31, H01L23/58
CPC Code(s): H01L23/562
Abstract: a semiconductor device and a method of forming the same are provided. the semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. the semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. each of the plurality of connectors has an elongated plan-view shape. a long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.
Inventor(s): Wei-Yu Chen of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Jen Lin of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Jan Pei of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Wei Chiu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin Liang Chen of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/73
Abstract: an embodiment is a device including a substrate comprising conductive pads, a package component bonded to the conductive pads of the substrate with solder connectors, the package component comprising an integrated circuit die, the integrated circuit die comprising die connectors, one of the solder connectors coupled to each of the die connectors and a corresponding conductive pad of the substrate, a first dielectric layer laterally surrounding each of the die connectors and a portion of the solder connectors, and a second dielectric layer being between the first dielectric layer and the substrate, the second dielectric layer laterally surrounding each of the conductive pads of the substrate.
Inventor(s): Ke-Gang Wen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Wei Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Chieh Hsiao of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/10, H01L23/00, H01L25/00, H10B80/00
CPC Code(s): H01L25/105
Abstract: an integrated semiconductor device is provided. the integrated semiconductor device includes a first semiconductor structure having a first ic, and a second semiconductor structure stacked above the first semiconductor structure and having a second ic. the second semiconductor structure has a first surface facing the first semiconductor structure and a second surface facing away from the first semiconductor structure. the integrated semiconductor device also includes a thermal dissipation structure having a first portion partially through the first ic and a second portion fully through the second semiconductor structure and exposed at the second surface of the second semiconductor structure. the second portion may be outside of the second ic.
Inventor(s): Hsi-Kuei Cheng of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Ching Fu Chang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Kang Han of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chieh Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/10, H01L21/48, H01L21/56, H01L21/683, H01L21/78, H01L23/498, H01L23/538, H01L25/00, H01L25/065, H01L25/16
CPC Code(s): H01L25/105
Abstract: an embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Kuo Hsia of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/16, G02B6/122, G02B6/13, H01L31/02, H01L31/0232, H01L31/18
CPC Code(s): H01L25/167
Abstract: a package includes an interposer structure including a first via; a first interconnect device including conductive routing and which is free of active devices; an encapsulant surrounding the first via and the first interconnect device; and a first interconnect structure over the encapsulant and connected to the first via and the first interconnect device; a first semiconductor die bonded to the first interconnect structure and electrically connected to the first interconnect device; and a first photonic package bonded to the first interconnect structure and electrically connected to the first semiconductor die through the first interconnect device, wherein the first photonic package includes a photonic routing structure including a waveguide on a substrate; a second interconnect structure over the photonic routing structure, the second interconnect structure including conductive features and dielectric layers; and an electronic die bonded to and electrically connected to the second interconnect structure.
Inventor(s): Chih-Chao CHOU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hsun CHIU of Zhubei city Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Wen CHANG of Jhubei city Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei TSAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/00, H01L23/00, H01L23/522, H01L23/528, H01L25/065
CPC Code(s): H01L25/50
Abstract: a package structure and a formation method are provided. the method includes disposing a first chip structure over a carrier substrate. the first chip structure has a front-side interconnection structure facing the carrier substrate. the method also includes forming a back-side interconnection structure over the first chip structure. the first chip structure has a device portion between the back-side interconnection structure and the front-side interconnection structure. the back-side interconnection structure has stacked conductive vias. the method further includes bonding a second chip structure to the first chip structure using dielectric-to-dielectric bonding and metal-to-metal bonding.
Inventor(s): Szu-Ying Chen of Toufen Township (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/00, H01L23/00, H01L23/522, H01L23/528, H01L23/58, H01L25/065, H01L25/18, H01L27/146
CPC Code(s): H01L25/50
Abstract: a chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. a plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. the plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. the plurality of metal pads includes active metal pads and dummy metal pads. the active metal pads are electrically coupled to the integrated circuits. the dummy metal pads are electrically decoupled from the integrated circuits.
Inventor(s): Wei-An LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Wei PENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Te-Hsin CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng TZENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Hsing WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, G06F30/39, H01L27/118
CPC Code(s): H01L27/0207
Abstract: a method includes fabricating active-region structures extending in a first direction on a substrate, and fabricating a plurality of gate-conductors extending in a second direction above the substrate. the method also includes fabricating a backside horizontal conducting line in a backside first conducting layer below the substrate and having the backside horizontal conducting line extending in the first direction across a vertical boundary of a circuit cell. the method further includes fabricating a pin-connector that is connected to the backside horizontal conducting line, and fabricating a backside vertical conducting line extending in the second direction in a backside second conducting layer below the backside first conducting layer. the pin-connector is directly connected between the backside horizontal conducting line and the backside vertical conducting line.
Inventor(s): Kam-Tou SIO of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng Tzeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Lin of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L21/84, H01L27/118, H01L27/12, H03K3/037
CPC Code(s): H01L27/0207
Abstract: an integrated circuit includes a first pair of power rails and a second pair of power rails that are disposed in a first layer, conductive lines disposed in a second layer above the first layer, and a first active area disposed in a third layer above the second layer. the first active area is arranged to overlap the first pair of power rails. the first active area is coupled to the first pair of power rails through a first line of the conductive lines and a first group of vias, and the first active area is coupled to the second pair of power rails through at least one second line of the conductive lines and a second group of vias different from the first group of vias.
Inventor(s): Po-Wei Fong of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Jong Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Te Liu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Ying Chen of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14612
Abstract: some embodiments relate to an integrated circuit including a plurality of floating diffusion regions ohmically connected to a common contact via a patterned conductive layer, obviating a need for individual contacts for each floating diffusion region. the integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. the interconnect structure includes a plurality of dielectric layers and a conductive layer that are stacked over one another in alternating fashion. a contact electrode is disposed over and in direct (e.g., direct and ohmic) contact with the conductive layer. the conductive layer is directly (e.g., directly and ohmically) connected to a respective surface of each of a plurality of floating diffusion regions. the respective surfaces connected by the conductive layer are co-planar with one another. each floating diffusion region can be associated with a respective pixel of an array of pixels of an image sensor.
Inventor(s): Chao-Te Liu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Chen Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Ying Chen of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Jong Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/1463
Abstract: in some embodiments, the present disclosure relates to a method for forming an image sensor and associated device structure. a fdti trench is formed from a frontside of a substrate between a first pixel region and a second pixel region and then filled to form a fdti structure. a cap layer is formed over the fdti structure overlying the first pixel region and the second pixel region of the substrate. a first photodiode is formed in the first pixel region and a second photodiode is formed in the second pixel region. a fd node is formed within the cap layer between the first pixel region and the second pixel region overlying the fdti structure. the fd node may be shared by a group of pixel regions not separated by the fdti structure, such that few metal contacts are needed and thus reduce parasitic capacitance issues of proximity metal contacts.
Inventor(s): Sin-Yao Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng Chieh Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shu Yen Kung of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Sheng Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/1464
Abstract: trenches for a back side deep trench isolation (bdti) structure are formed using two etches: a high-aspect ratio etch and a mouth etch. the trenches have an upper part (the mouth) that is wider and the lower part of the trenches. the lower part is narrower and has a higher aspect ratio than the upper part. the trenches exhibit a step change in width between the upper part and the lower part. the depth of the lower part may be fixed to provide an aspect ratio that is high but limited to an aspect ratio at which the lower part may be consistently filled without creating voids. the overall depth of the trenches may be varied by adjusting the depth of the mouth area. the resulting bdti structure provides an image sensor with better optical performance characteristics than may be achieved using a single trench etch.
Inventor(s): Ming-Heng TSAI of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Sheng LIANG of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/423, H01L29/786, H01L29/788
CPC Code(s): H01L29/0673
Abstract: a semiconductor device structure includes first nanostructures formed over a substrate. the structure also includes second nanostructures formed over the substrate. the structure also includes a wall structure formed between the first nanostructures and the second nanostructures. the structure also includes a gate structure formed across the first nanostructures, the second nanostructures, and the wall structure. the wall structure includes a main portion and an extending portion, and the main portion is in direct contact with the first nanostructures and the second nanostructures. the extending portion protrudes from the sidewalls of the second nanostructures.
Inventor(s): Kuan-Ting PAN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Lun CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/08, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a semiconductor structure and a method for forming the same are provided. the semiconductor device structure includes a substrate having a first region and a second region, and a plurality of first nanostructures stacked in a vertical direction in the first region. the semiconductor device structure includes a plurality of second nanostructures stacked in the vertical direction in the second region, and a silicon germanium (sige) layer formed below the first nanostructures in the first region. the semiconductor device structure also includes a first gate structure surrounding the first nanostructures in the first region, and a second gate structure surrounding the second nanostructures in the second region. the bottommost surface of the second gate structure is lower than the bottommost surface of the first gate structure.
Inventor(s): Shu-Han Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Ju Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Heng Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/02, H01L21/265, H01L21/306, H01L21/311, H01L21/3115, H01L29/10, H01L29/66, H01L29/78
CPC Code(s): H01L29/0673
Abstract: in an embodiment, a structure includes: a nano-structure; an epitaxial source/drain region adjacent the nano-structure; a gate dielectric wrapped around the nano-structure; a gate electrode over the gate dielectric, the gate electrode having an upper portion and a lower portion, a first width of the upper portion increasing continually in a first direction extending away from a top surface of the nano-structure, a second width of the lower portion being constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source/drain region.
Inventor(s): Chien-I Kuo of Chiayi County (TW) for taiwan semiconductor manufacturing company, ltd., Wei Hao Lu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Li Su of ChuBei City (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L21/8234, H01L29/06, H01L29/66, H01L29/78
CPC Code(s): H01L29/0847
Abstract: a method of forming a semiconductor includes forming a first recess in a first semiconductor fin protruding from a substrate and forming a second recess in a second semiconductor fin protruding from the substrate first semiconductor fin and forming a source/drain region in the first recess and the second recess. forming the source/drain region includes forming a first portion of a first layer in the first recess and forming a second portion of the first layer in the second recess, forming a second layer on the first layer by flowing a first precursor, and forming a third layer on the second layer by flowing a second precursor, the third layer being a single continuous material.
Inventor(s): Chi-Ming Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuei-Ming Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/15, H01L21/02, H01L29/20, H01L29/66, H01L29/778
CPC Code(s): H01L29/157
Abstract: various embodiments of the present disclosure are directed towards an integrated chip a semiconductor device including a plurality of superlattice layers disposed over a substrate. the plurality of superlattice layers include a first superlattice layer overlying a second superlattice layer. a channel layer overlies the plurality of superlattice layers. an active layer overlies the channel layer. a first interlayer buffer layer is disposed directly between the first superlattice layer and the second superlattice layer. the first interlayer buffer layer comprises a first density of dislocations greater than a second density of dislocations in the first superlattice layer.
Inventor(s): JHON JHY LIAW of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/41733
Abstract: the present disclosure relates to methods for forming self-aligned source/drain contacts with increased contact size while maintaining the reliability margin between source/drain contacts and gate electrodes. semiconductor devices according to the present disclosure has contact landing rc reduction at source/drain contacts as well as device performance improvement. the source/drain contacts formed according to the present disclosure also has lowered height leading to the capacitance reduction of between the source/drain contact to gate electrode. embodiments of the present disclosure also provides improvements in circuit density and process margin. the self-aligned contact scheme according to the present disclosure allow more aggressive gate pitch (cpp) scaling and also maintain the landing area as well as contact-gate isolation margin.
Inventor(s): Hong-Chih CHEN of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jhon-Jhy LIAW of Zhudong (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/417, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/41775
Abstract: semiconductor structures and methods for manufacturing the same are provided. the semiconductor structure includes a gate structure formed over a substrate, and a source/drain (s/d) structure formed adjacent to the gate structure. the semiconductor structure includes a first dielectric layer formed over the s/d structure, and an s/d contact structure formed over the s/d structure. the s/d contact structure penetrates through the first dielectric layer, and a top surface of the gate structure is higher than a top surface of the s/d contact structure.
Inventor(s): Sheng-Jier YANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L27/088, H01L29/06, H01L29/40, H01L29/423, H01L29/45, H01L29/66, H01L29/786
CPC Code(s): H01L29/41775
Abstract: in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched thereby forming a source/drain space, a stressor layer is formed in the source/drain space, a metal gate structure including part of the second semiconductor layer as channel regions is formed by a gate replacement process, after the metal gate structure is formed, the stressor layer is at least partially removed, and a source/drain contact comprising metal or a metallic material is formed in the source/drain space from which the stressor layer is at least partially removed.
Inventor(s): Ruoh-Ning TZENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Hua PAN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8234, H01L29/66, H01L29/78
CPC Code(s): H01L29/41791
Abstract: structures and formation methods of a semiconductor device structure are provided. the semiconductor device structure includes a gate electrode layer formed over a substrate and a gate spacer structure formed over a sidewall of the gate electrode layer. the semiconductor device structure also includes a source/drain contact structure adjacent to the gate spacer structure and separated from the gate electrode layer by the gate spacer structure. the source/drain contact structure includes a conductive base portion formed over a source/drain region in the substrate and a conductive capping portion with an arched top surface formed over the conductive base portion. the top surface of the conductive base portion is lower than the top surface of the gate electrode layer. the semiconductor device structure further includes a first dielectric capping layer formed over the source/drain contact structure.
Inventor(s): Shen-Yang Lee of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Pi Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Lin Chao of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Pinyen Lin of Rochester NY (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L27/088, H01L29/06, H01L29/24, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L29/42392
Abstract: gate stack fabrication techniques are disclosed for capacitance equivalent thickness scaling. an exemplary method for forming a gate stack includes forming an interfacial layer, forming a high-k dielectric layer over the interfacial layer, and forming an electrically conductive gate layer over the high-k dielectric layer. forming the high-k dielectric layer includes forming a group 4 element-containing dielectric layer (e.g., an hfolayer and/or a zrolayer) and forming a rare earth element-containing dielectric layer. in some embodiments, the rare earth element-containing dielectric layer includes yttrium and oxygen, nitrogen, carbon, or a combination thereof. the electrically conductive gate layer is formed over the rare earth element-containing dielectric layer (i.e., the rare earth element-containing dielectric layer is not removed and remains in the gate stack). the rare earth element-containing dielectric layer can be formed before, after, or between forming sublayers of group 4 element-containing dielectric layer.
Inventor(s): I-Hsieh Wong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang Lee of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Pin Lin of Xinpu Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L29/06, H01L29/417, H01L29/66, H01L29/786
CPC Code(s): H01L29/42392
Abstract: embodiments utilize a two layer inner spacer structure during formation of the inner spacers of a nano-fet device. the materials of the first inner spacer layer and second inner spacer layer can be selected to have a mismatch in their coefficients of thermal expansion (cte). as the structure cools after deposition, the inner spacer layer which has a larger cte will exhibit compressive stress on the other inner spacer layer, however, because the two layers have a common interface, the layer with the smaller cte will exhibit a counter acting tensile stress.
Inventor(s): Chi-Hsing Hsu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Min Cao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/51, H01L21/02, H01L21/8238, H01L27/092, H01L29/06
CPC Code(s): H01L29/516
Abstract: a first fin structure is disposed over a substrate. the first fin structure contains a semiconductor material. a gate dielectric layer is disposed over upper and side surfaces of the first fin structure. a gate electrode layer is formed over the gate dielectric layer. a second fin structure is disposed over the substrate. the second fin structure is physically separated from the first fin structure and contains a ferroelectric material. the second fin structure is electrically coupled to the gate electrode layer.
Inventor(s): Hsu Ming HSIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Hao TSAO of Taichung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/775, H01L29/06, H01L29/423, H01L29/66
CPC Code(s): H01L29/775
Abstract: a semiconductor device, along with methods of forming such, are described. the device includes a semiconductor material disposed over a substrate, a first epitaxial source/drain region in contact with a first end of the semiconductor material, a second epitaxial source/drain region in contact with a second end opposite the first end of the semiconductor material, a first dummy gate dielectric layer in contact with the semiconductor material and the first epitaxial source/drain region, a second dummy gate dielectric layer in contact with the semiconductor material and the second epitaxial source/drain region, and an interfacial dielectric disposed between the first and second dummy gate dielectric layers.
Inventor(s): Chun-Chieh WANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ting LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yueh-Ching PAI of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chieh CHANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Huai-Tei YANG of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L21/3065, H01L21/3105, H01L21/311, H01L21/32, H01L21/768, H01L21/8234, H01L21/8238, H01L27/088, H01L29/06, H01L29/08, H01L29/66
CPC Code(s): H01L29/7856
Abstract: a semiconductor structure and a method for forming the same are provided. the semiconductor structure includes a gate structure formed over a fin structure, and a gate spacer layer formed on a sidewall surface of the gate structure. the semiconductor structure includes a source/drain (s/d) epitaxial layer formed adjacent to the gate structure, and a dielectric spacer layer formed on the s/d epitaxial layer. the semiconductor structure includes a contact plug barrier formed over the s/d epitaxial layer, and a contact plug surrounding by the contact plug barrier, wherein the contact plug is separated from the gate spacer layer by the dielectric spacer layer and the contact plug barrier.
Inventor(s): Huaixin XIAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Qingchao MENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yang ZHOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Chih HSIEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K3/037, H01L27/105, H01L29/02, H01L29/06, H01L29/10, H01L29/417, H03K3/288, H03K3/289, H03K3/356, H03K3/3562
CPC Code(s): H03K3/0372
Abstract: an integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. the transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. the gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit. the second time delay circuit further includes a second gate-conductor and a second gate via-connector in direct contact with the second gate-conductor. the second gate-conductor intersects a first-type active region structure and a second-type active region structure in a second area, and wherein at least a portion of the second gate via-connector is atop the second-type active region structure
Inventor(s): Tsung-Hsin YU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Nick PAI of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Bo-Ting CHEN of Fengyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K17/16, H03K19/003, H03K19/0175
CPC Code(s): H03K17/162
Abstract: circuits and methods for preventing glitch in a circuit are disclosed. in one example, a circuit coupled to an input/output pad is disclosed. the circuit includes: a first level shifter, a second level shifter, and a control logic circuit. the first level shifter is configured for generating a data signal. the second level shifter is configured for generating an output enable signal. the first and second level shifters are controlled by first and second power-on-control signals, respectively. the control logic circuit is coupled to the first level shifter and the second level shifter.
Inventor(s): Yi Yun Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Feng Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., SiLiang Xie of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., PingPing Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Qingchao Meng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K19/0185, H03K19/00, H03K19/0948
CPC Code(s): H03K19/018521
Abstract: a delay-enhanced inverter circuit (de-inverter) includes: a non-delay-enhanced inverter circuit (ne-inverter) having an output at a first node and an input at a second node; and a capacitive device feedback-coupled between the first node and the second node. the capacitive device includes: a first positive-channel metal-oxide (pmos) field-effect transistor (fet) (pfet) feedback-coupled between the first node and the second node, the first pfet having a capacitor-configuration; and a first negative-channel metal-oxide (nmos) fet (nfet) feedback-coupled feedback-between the first node and the first reference voltage, the first nfet having a capacitor-configuration.
Inventor(s): Meng-Sheng Chang of Chu-bei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En Huang of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B20/20, H01L29/06
CPC Code(s): H10B20/20
Abstract: a semiconductor device includes a plurality of first nanostructures extending along a first lateral direction. the semiconductor device includes a first epitaxial structure and second epitaxial structure respectively coupled to ends of each of the plurality of first nanostructures along the first lateral direction. the semiconductor device includes a dielectric fin structure disposed immediately next to a sidewall of each of the plurality of first nanostructures facing a second lateral direction perpendicular to the first lateral direction. the semiconductor device includes a first gate structure wrapping around each of the plurality of first nanostructures except for the sidewalls of the first nanostructures. the semiconductor device includes a metal structure disposed above the first gate structure and coupled to one of the first or second epitaxial structure.
Inventor(s): Meng-Sheng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Jen YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Tung PENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-I HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B20/25
CPC Code(s): H10B20/25
Abstract: an integrated circuit includes a first active region, a second active region, a first fuse and a dummy fuse. the first active region extends in a first direction, and is on a first level. the second active region extends in the first direction, is on the first level, and is separated from the first active region in a second direction different from the first direction. the first fuse extends in the first direction, is on a second level, overlaps the first active region and is electrically coupled to the first active region. the dummy fuse extends in the first direction, is on the second level, and is separated from the first fuse in the second direction. the dummy fuse overlaps the second active region, and is not electrically coupled to the second active region.
Inventor(s): Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Bo-Feng Young of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Han-Jong Chia of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chen Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Cheng Yang of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/20, G11C7/18, G11C11/14, H10B51/10
CPC Code(s): H10B51/20
Abstract: a method of forming a ferroelectric random access memory (feram) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.
Inventor(s): Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yu Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Han-Jong Chia of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B63/00, H01L21/02, H01L21/822, H01L21/8234, H01L27/06, H01L29/06, H01L29/24, H01L29/423, H01L29/66, H01L29/786, H01L29/861, H10B43/20, H10B43/35, H10N70/00, H10N70/20
CPC Code(s): H10B63/84
Abstract: memory devices and methods of forming the memory devices are disclosed herein. the memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. the memory devices further include a first diode and a second diode over the inter-metal dielectric layer. the memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.
Inventor(s): Kuo-Feng Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Bo-Hung Lin of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Harry-Haklay Chuang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuei-Hung Shen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ding-Shuo Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Jen Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/10, G11C11/16, H01F10/32, H10N50/01, H10N50/85
CPC Code(s): H10N50/10
Abstract: an integrated chip including a reference magnetic layer and a barrier layer over the reference magnetic layer. a first free magnetic layer is over the barrier layer. a second free magnetic layer is over the first free magnetic layer. a spacer layer is between the first free magnetic layer and the second free magnetic layer. the spacer layer includes magnesium and a transition metal. an atomic ratio of the magnesium to the transition metal ranges from 15% to 80%.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on August 8th, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- B32B37/18
- CPC B32B37/18
- Taiwan semiconductor manufacturing company, ltd.
- B81B7/04
- B81C1/00
- B81C3/00
- CPC B81B7/04
- G02B6/12
- G02B6/13
- CPC G02B6/12004
- G02B6/42
- H01L25/16
- CPC G02B6/4214
- G03F1/24
- G03F1/70
- G03F7/20
- CPC G03F1/24
- G03F7/004
- G03F7/038
- G03F7/32
- H01L21/027
- H01L21/47
- CPC G03F7/0048
- G06F30/3323
- G06N3/08
- CPC G06F30/3323
- G11C17/18
- G11C7/18
- H10B20/00
- CPC G11C17/18
- H01L21/02
- C23C16/40
- C23C16/56
- H01L21/3105
- CPC H01L21/02337
- H01L29/08
- H01L29/66
- H01L29/78
- CPC H01L21/0245
- H01L21/3065
- H01J37/32
- H01L21/683
- CPC H01L21/3065
- H01L21/48
- C25D5/00
- H01L23/00
- H01L23/498
- H01L23/538
- CPC H01L21/4853
- H01L21/67
- B65G47/90
- G01V8/12
- CPC H01L21/67265
- H01L21/762
- H01L21/8238
- H01L27/088
- CPC H01L21/76224
- H01L21/768
- H01L21/306
- H01L21/311
- CPC H01L21/76816
- C08F10/02
- C08F10/06
- C08F20/06
- C08F20/32
- H01L23/532
- CPC H01L21/7682
- H01L23/522
- CPC H01L21/76883
- CPC H01L21/76897
- H01L23/48
- CPC H01L21/76898
- H01L21/8234
- CPC H01L21/823431
- CPC H01L21/823481
- B82Y10/00
- H01L29/06
- H01L29/423
- H01L29/775
- H01L29/786
- H01L27/092
- H01L29/10
- CPC H01L21/823821
- H01L21/033
- CPC H01L21/823878
- H01L21/66
- G01N23/2251
- CPC H01L22/12
- H01L23/367
- H01L21/56
- H01L21/78
- H01L23/29
- H01L23/31
- H01L25/00
- H01L25/065
- CPC H01L23/3675
- CPC H01L23/3677
- H01L23/528
- CPC H01L23/5226
- H01L23/46
- H01L29/40
- H01L29/417
- CPC H01L23/528
- CPC H01L23/5329
- H01L25/18
- CPC H01L23/5386
- H01L25/10
- CPC H01L23/5389
- CPC H01L23/562
- H01L23/58
- CPC H01L24/73
- H10B80/00
- CPC H01L25/105
- G02B6/122
- H01L31/02
- H01L31/0232
- H01L31/18
- CPC H01L25/167
- CPC H01L25/50
- H01L27/146
- H01L27/02
- G06F30/39
- H01L27/118
- CPC H01L27/0207
- H01L21/84
- H01L27/12
- H03K3/037
- CPC H01L27/14612
- CPC H01L27/1463
- CPC H01L27/1464
- H01L29/788
- CPC H01L29/0673
- H01L21/265
- H01L21/3115
- CPC H01L29/0847
- H01L29/15
- H01L29/20
- H01L29/778
- CPC H01L29/157
- CPC H01L29/41733
- CPC H01L29/41775
- H01L29/45
- CPC H01L29/41791
- H01L29/24
- CPC H01L29/42392
- H01L29/51
- CPC H01L29/516
- CPC H01L29/775
- H01L21/32
- CPC H01L29/7856
- H01L27/105
- H01L29/02
- H03K3/288
- H03K3/289
- H03K3/356
- H03K3/3562
- CPC H03K3/0372
- H03K17/16
- H03K19/003
- H03K19/0175
- CPC H03K17/162
- H03K19/0185
- H03K19/00
- H03K19/0948
- CPC H03K19/018521
- H10B20/20
- CPC H10B20/20
- H10B20/25
- CPC H10B20/25
- H10B51/20
- G11C11/14
- H10B51/10
- CPC H10B51/20
- H10B63/00
- H01L21/822
- H01L27/06
- H01L29/861
- H10B43/20
- H10B43/35
- H10N70/00
- H10N70/20
- CPC H10B63/84
- H10N50/10
- G11C11/16
- H01F10/32
- H10N50/01
- H10N50/85
- CPC H10N50/10
