Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on August 22nd, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on August 22nd, 2024
Taiwan Semiconductor Manufacturing Company, Ltd.: 69 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L29/66 (14), H01L21/768 (14), H01L23/522 (11), H01L27/092 (11), H01L29/06 (10) H01L21/823481 (3), H10N70/231 (2), H01L23/5226 (2), H10B10/125 (2), H01L23/562 (2)
With keywords such as: layer, structure, dielectric, semiconductor, disposed, forming, substrate, device, gate, and conductive in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s): Yi-Chen HO of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Chih Ping LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ker-Hsun LIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hsun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B08B9/032, B08B13/00
CPC Code(s): B08B9/0321
Abstract: a method of cleaning includes placing a semiconductor device manufacturing tool component made of quartz on a support. a cleaning fluid inlet line is attached to a first open-ended tubular quartz projection extending from an outer main surface of the semiconductor device manufacturing tool component. a cleaning fluid is applied to the semiconductor device manufacturing tool component by introducing the cleaning fluid through the cleaning fluid inlet line and the tubular quartz projection.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sey-Ping Sun of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih Wei Liang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/13
CPC Code(s): G02B6/131
Abstract: optical devices and methods of manufacture are provided which form a first active layer of optical devices. after the first active layer of optical devices is formed, a second active layer of optical devices is manufactured over the first active layer of optical devices, wherein the second active layer of optical devices is formed to create the optical devices with crystalline material.
Inventor(s): Tsung-Fu Tsai of Changhua (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Wei Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Jen Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4206
Abstract: a method includes connecting a photonic package to a substrate, wherein the photonic package includes a waveguide and an edge coupler that is optically coupled to the waveguide; connecting a semiconductor device to the substrate adjacent the photonic package; depositing a first protection material on a first sidewall of the photonic package that is adjacent the edge coupler; encapsulating the photonic package and the semiconductor device with an encapsulant; performing a first sawing process through the encapsulant and the substrate, wherein the first sawing process exposes the first protection material; and removing the first protection material to expose the first sidewall of the photonic package.
Inventor(s): Feng-Wei KUO of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chewn-Pu Jou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Kuo Hsia of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei TSENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42, G02B6/293
CPC Code(s): G02B6/4215
Abstract: a package structure comprises photonic dies and an interposer structure. each photonic die includes a dielectric layer and a first grating coupler embedded in the dielectric layer. the interposer structure is disposed below the photonic dies. the interposer structure includes an oxide layer and a second grating coupler embedded in the oxide layer. the photonic dies are optically coupled through the first grating couplers of the photonic dies and the second grating coupler of the interposer structure.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jiun Yi Wu of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4283
Abstract: a method includes forming a first redistribution structure on a first substrate; forming a waveguide structure on a second substrate, wherein the waveguide structure includes waveguides; bonding the waveguide structure to the redistribution structure using dielectric-to-dielectric bonding; removing the second substrate; forming a second redistribution structure on the waveguide structure; and connecting a photonic package to the second redistribution structure, wherein the photonic package is optically coupled to the waveguides.
Inventor(s): Yun-Yue LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/64, G03F1/22
CPC Code(s): G03F1/64
Abstract: a method for forming a structure of a pellicle-mask structure is provided. the method includes forming a mask pattern on a mask substrate. the method also includes bonding a pellicle frame to the mask pattern through a pellicle frame adhesive. the method further includes forming a vent structure in the pellicle frame. in addition, the method includes bonding a pellicle membrane to the pellicle frame. the pellicle membrane includes a peripheral portion over the pellicle frame and a top membrane portion over the peripheral portion, and a lateral width of the peripheral portion of the pellicle membrane is greater than a lateral width of the pellicle frame adhesive.
Inventor(s): Tzu-Yang LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yuansun Village (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hsiang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/039, B82Y30/00, B82Y40/00, G03F7/004, G03F7/038, G03F7/20, G03F7/30, G03F7/32, G03F7/36, G03F7/38, G03F7/40
CPC Code(s): G03F7/0397
Abstract: a photoresist composition includes a photoactive compound and a polymer. the polymer has a polymer backbone including one or more groups selected from:
Inventor(s): Tzu-Yang LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yuansun Village (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hsiang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/039, B82Y30/00, B82Y40/00, G03F7/004, G03F7/038, G03F7/20, G03F7/30, G03F7/32, G03F7/36, G03F7/38, G03F7/40
CPC Code(s): G03F7/0397
Abstract:
Inventor(s): Tzu-Yang LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu CHANG of Yuansun Village (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hsiang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/039, B82Y30/00, B82Y40/00, G03F7/004, G03F7/038, G03F7/20, G03F7/30, G03F7/32, G03F7/36, G03F7/38, G03F7/40
CPC Code(s): G03F7/0397
Abstract: the polymer backbone includes at least one group selected from b, c-1, or c-2, wherein alg is an acid labile group, and x is a linking group.
Inventor(s): Shih-Ming CHANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chiu-Hsiang CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ru-Gun LIU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, G03F7/20
CPC Code(s): G03F7/70341
Abstract: a method of operating a semiconductor apparatus includes generating an air flow that flows from a covering structure; causing a photomask to move over the covering structure such that particles attached to the photomask are blown away from the photomask by the air flow; and irradiating the photomask with light through a light transmission region of the covering structure.
Inventor(s): Tai-Hao Wen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Fan Chang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Win-San Khwa of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/10, G06F7/501, G06F7/544, G11C7/12
CPC Code(s): G11C7/1069
Abstract: a memory system and operating method for controlling the same are provided. the memory system includes a memory array and a control circuit. the memory array comprising a first memory block and a second memory block, wherein the first memory block has a longer endurance than the second memory block. the control circuit is configured to receive a neural network model having a plurality of weight data; divide each of the plurality of weight data into a first data segment and a second data segment, wherein the first data segment has a higher bit order than the second data segment; and program the plurality of first data segments on the first memory block and program the plurality of second data segments on the second memory block.
Inventor(s): Wei-Xiang YOU of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Szuya LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yin WANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/412, G11C11/419, H03K19/20, H10B10/00
CPC Code(s): G11C11/412
Abstract: an sram cell includes a first inverter cross-coupled to a second inverter. the first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. the sram cell further includes a first n-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. the sram cell further includes a first p-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. the sram cell further includes a p-type transistor having a third drain, coupled to a second gate of the first p-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.
Inventor(s): Po-Tang Tseng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Heng Yen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tai-Kun Kao of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Tai Peng of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01J27/08, H01J27/02, H01J37/317, H01L21/26
CPC Code(s): H01J27/08
Abstract: an assembly present in an ion source for supporting an arc chamber upon a base plate includes a first arc support plate, a first screw, and a second screw. the first screw passes through a smooth through-hole in an arm of the first arc support plate and extends into a bore in the base plate. the second (or adjustable) screw passes through a threaded through-hole in an arm of the first arc support plate and engages an upper surface of the base plate itself, and can be used to change the altitude and angle of the first arc support plate relative to the base plate. this adjustment ability improves the beam quality of the ion source.
Inventor(s): Yi-Chen Lo of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ding-Kang Shih of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsungyu Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Ling Pai of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Pang-Yen Tsai of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Te Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pinyen Lin of Rochester NY (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, H01L21/768, H01L21/8238, H01L23/532, H01L27/092, H01L29/08, H01L29/40, H01L29/66, H01L29/775
CPC Code(s): H01L21/02068
Abstract: in an embodiment, a method includes forming a first semiconductor fin and a second semiconductor fin over a front-side of a substrate; etching a first recess in the first semiconductor fin and a second recess in the second semiconductor fin; forming a first epitaxial region in the first recess and first epitaxial nodules along sidewalls of the first recess; forming a second epitaxial region in the second recess and second epitaxial nodules along sidewalls of the second recess; flowing first precursors to remove the first epitaxial nodules; depositing an interlayer dielectric over the first epitaxial region and the second epitaxial region; etching a first opening in the interlayer dielectric to expose the first epitaxial region; forming a first epitaxial cap on the first epitaxial region and third epitaxial nodules over the interlayer dielectric; and flowing second precursors to remove the third epitaxial nodules.
Inventor(s): Wan-Lin Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Hau Shiu of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jen Hung Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shing-Chyang Pan of Jhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, C23C14/06, C23C14/08, C23C14/22, C23C16/02, C23C16/04, C23C16/30, C23C16/40, C23C16/455, H01J37/32, H01L21/033, H01L21/308, H01L21/311, H01L21/768, H01L21/8238, H01L23/528, H01L29/66
CPC Code(s): H01L21/02126
Abstract: a method of manufacturing a semiconductor device includes depositing a dielectric layer over a substrate, performing a first patterning to form an opening in the dielectric layer, and depositing an oxide film over and contacting the dielectric layer and within the opening in the dielectric layer. the oxide film is formed from multiple precursors that are free of o, and depositing the oxide film includes forming a plasma of a first precursor of the multiple precursors.
Inventor(s): Jian-Jou Lian of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Wen Hsu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Neng-Jye Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Min Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Wei Wu of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lin Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Bin Huang of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/027, G03F7/09, G03F7/095, G03F7/20, G03F7/32, H01L21/02, H01L21/033, H01L21/306, H01L21/311
CPC Code(s): H01L21/0273
Abstract: a semiconductor device and method of manufacture are provided. after a patterning of a middle layer, the middle layer is removed. in order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.
Inventor(s): Yen-Yu CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Cheng LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chen KUO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jr-Hung LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hui WENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yahru CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/027, H01L21/308, H01L21/311
CPC Code(s): H01L21/0274
Abstract: a method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate and forming a dehydrated film over the photoresist layer. the photoresist layer is selectively exposed to actinic radiation to form an exposed portion and an unexposed portion of the photoresist layer. the photoresist layer is developed to remove the unexposed portion of the photoresist layer and a first portion of the dehydrated film over the unexposed portion of the photoresist layer. in an embodiment, the method includes etching the substrate by using the exposed portion of the photoresist layer as a mask.
Inventor(s): Wei-Chao CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yong-Jin LIOU of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Wei CHANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Sen KUO of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Jia SHIU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/308, H01L21/027, H01L21/266, H01L21/66, H01L27/146
CPC Code(s): H01L21/3086
Abstract: a method of fabricating a semiconductor device includes determining a concentration of a byproduct in a photoresist composition. a photoresist layer is formed over a substrate using the photoresist composition when the concentration of the byproduct is below a threshold value. a photoresist pattern is formed in the photoresist layer exposing a portion of the substrate, and an operation is performed on the exposed portion of the substrate.
Inventor(s): Lung-Kun CHU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jia-Ni YU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Fu LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/477, H01L21/475, H01L21/4757, H01L27/088
CPC Code(s): H01L21/477
Abstract: a method for processing an integrated circuit includes forming a plurality of transistors. the method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. this process can be repeated to produce a plurality of transistors each having different threshold voltages.
Inventor(s): Han-Hsiang Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Hsien Wen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Yu Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/48, H01L23/00, H01L23/498
CPC Code(s): H01L21/4857
Abstract: a method includes providing a semiconductor chip with a plurality of first connector structures disposed on a topmost one of a plurality of metallization layers. the method includes forming a redistribution structure comprising a plurality of conductive layers and a plurality of via structures, adjacent ones of the plurality of conductive layers being connected through at least a corresponding one of the plurality of via structures. the method includes bonding the plurality of first connector structures to the redistribution structure. the method includes bonding the redistribution structure to a carrier substrate through a plurality of second connector structures. forming the redistribution structure includes laterally rotating a first one of the plurality of via structures around a second one of the plurality of via structures, the first via structure being vertically above the second via structure.
Inventor(s): Jyh-Shiou HSU of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Jeng-Shin MA of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Lung WU of Zhunan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/677, B65G47/90, H01L21/673
CPC Code(s): H01L21/67772
Abstract: a wafer transport carrier includes various components to provide improved air sealing to reduce air leakage into the wafer transport carrier. the wafer transport carrier may include a housing having a hollow shell that contains a vacuum or an inert gas to minimize and/or prevent humidity and oxygen ingress into the wafer transport carrier, a wafer rack that is integrated into the shell of the housing to minimize and/or prevent air leakage around the wafer rack, and/or an enhanced magnet-based door latch to provide air sealing around the full perimeter of the opening of the housing. these components and/or additional components described herein may reduce and/or prevent debris, moisture, and/or other types of contamination from the semiconductor fabrication facility from entering the wafer transport carrier and causing wafer defects and/or device failures.
Inventor(s): Hung-Yu YEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Chu LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/532, H01L29/66
CPC Code(s): H01L21/7682
Abstract: a method for manufacturing a semiconductor device includes: forming on a substrate, a structure including a plurality of dielectric spacers and a plurality of dielectric portions that are disposed to form a plurality of recesses, such that each of the recesses is formed between a corresponding one of the dielectric spacers and a corresponding one of the dielectric portions; and subjecting the dielectric spacers and the dielectric portions to a plasma treatment process such that the dielectric spacers and the dielectric portions are deformed to form a plurality of capping portions to cap the recesses, respectively, so as to form a plurality of air gaps.
Inventor(s): Hsi-Wen TIEN of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Hao LIAO of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Teng DAI of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chieh YAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei LU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Ju LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/033, H01L23/522, H01L23/528, H01L23/532
CPC Code(s): H01L21/7682
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes includes a first insulating layer formed over a semiconductor substrate and conductive vias formed in the first insulating layer. the conductive structure also includes conductive lines and air gaps alternately formed over the first insulating layer. the conductive lines are correspondingly aligned to the conductive vias. the conductive structure further includes capping layers correspondingly covering the plurality of air gaps.
Inventor(s): Po-Kuan HO of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Tien WU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/528, H01L23/532
CPC Code(s): H01L21/76843
Abstract: a method includes providing a semiconductor structure including a dielectric layer having an opening exposing a top surface of a metal layer. a bottom via is selectively deposited in the opening and over the metal layer. a barrier layer is deposited over the bottom via and in contact with the dielectric layer at a sidewall of the opening. a top via is formed in the opening, in contact with the barrier layer, and over the bottom via. the top via is separated from the dielectric layer by the barrier layer.
Inventor(s): Chun-Hsien Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., I-Li Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Wen Chen of Keelung City (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Chen Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Jung Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsing Tsai of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/532
CPC Code(s): H01L21/76861
Abstract: a method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. the first treatment is performed through the opening, and the first treatment is performed using a first process gas. after the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. a second metallic feature is deposited in the opening
Inventor(s): Peng-Soon LIM of Johor (MY) for taiwan semiconductor manufacturing company, ltd., Chung-Liang Cheng of Changhua County 500 (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Lin Chao of Hillsboro OR (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/8234, H01L23/522, H01L27/088
CPC Code(s): H01L21/76871
Abstract: a semiconductor device with liner-free contact structures and a method of fabricating the same are disclosed. the method includes forming first and second source/drain (s/d) regions on first and second fin structures, forming a first dielectric layer between the first and second s/d regions, forming first and second gate-all-around (gaa) structures on the first and second fin structures, forming a second dielectric layer on the first and second gaa structures and the first dielectric layer, forming a tapered trench opening in the second dielectric layer and on the first and second gaa structures and the first dielectric layer, selectively forming a seed layer on top surfaces of the first and second gaa structures and the first dielectric layer that are exposed in the tapered trench opening, and selectively depositing a conductive layer on the seed layer to fill the tapered trench opening.
Inventor(s): Dian-Hau CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Chiu HUANG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiang-Ku SHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., ShuFang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Yao LAI of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Ling CHANG of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Feng LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Peng-Chung JANGJIAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jo-Lin LAN of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Fang-I Chih of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/02, H01L23/522
CPC Code(s): H01L21/76873
Abstract: a method of forming a semiconductor structure includes forming a seed layer on a substrate, forming a photoresist layer on the seed layer with a first opening wider than a second opening, performing an electroplating process with a first plating current to grow a bottom portion of a first metal line in the first opening and a bottom portion of a second metal line in the second opening, continuing the electroplating process with a second plating current that is larger than the first plating current to grow a top portion of the first metal line and a top portion of the second metal line, removing the photoresist layer to expose a portion of the seed layer, and removing the exposed portion of the seed layer.
Inventor(s): Yu-An CHEN of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., I-Chang LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yuan TING of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/02, H01L21/311, H01L29/40
CPC Code(s): H01L21/76877
Abstract: an interconnect structure, along with methods of forming such, are described. in some embodiments, the method includes forming a first dielectric layer over one or more devices, forming a first conductive feature in the first dielectric layer, and forming two dielectric features over the first dielectric layer and the first conductive feature. at least one of the two dielectric features has a first width, and each dielectric feature includes a first low-k dielectric layer, an oxide layer, and a first etch stop layer. the method further includes forming a second conductive feature between the two dielectric features, and the second conductive feature has a second width substantially the same as the first width.
Inventor(s): Hui Hung Kuo of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Hsin Fu Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin Heng Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/02, H01L21/311, H01L21/3213, H01L21/56, H01L29/06
CPC Code(s): H01L21/823481
Abstract: provided are device with stepped isolation regions and methods for fabricating the same. an exemplary method includes forming mask segments over a semiconductor material; etching the semiconductor material to form first trenches, wherein the first trenches have a first trench maximum width and a first trench depth; forming a coating in the first trenches, wherein the coating has a coating depth less than the first trench depth, and wherein uncovered portions of the semiconductor material extend from the coating to the patterned masks; performing an etch process to etch the mask segments and the uncovered portions of the semiconductor material to form second trenches over the first trenches, wherein the second trenches have a second minimum width greater than the first maximum width and a second depth less than the first depth; and removing the coating from the first trenches.
Inventor(s): Shih-Wen Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jaming Chang of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Kai Hung Cheng of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hui Lin of Dajia Township (TW) for taiwan semiconductor manufacturing company, ltd., Jei Ming Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/02, H01L21/762, H01L27/088, H01L29/06
CPC Code(s): H01L21/823481
Abstract: methods of cutting fins, and structures formed thereby, are described. in an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. the first fin and the second fin are longitudinally aligned. the fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. the insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. the insulating liner includes a material with a band gap greater than 5 ev.
Inventor(s): Shu-Wen SHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Ping CHEN of Toucheng Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L21/823481
Abstract: in a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first and second semiconductor layers and a hard mask layer over the stacked layer is formed. a sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. an etching is performed to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on sidewalls of the exposed hard mask layer and stacked layer. a first dielectric layer and a second dielectric layer made of a different material than the first dielectric layer are formed. the second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer. during the etching operation, a protection layer is formed over the sacrificial cladding layer.
Inventor(s): Shahaji B. More of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/285, H01L27/092, H01L29/06, H01L29/08, H01L29/417, H01L29/45, H01L29/66, H01L29/78
CPC Code(s): H01L21/823814
Abstract: a method includes forming isolation regions extending into a semiconductor substrate, and forming a first plurality of protruding fins and a second protruding fin over the isolation regions. the first plurality of protruding fins include an outer fin farthest from the second protruding fin, and an inner fin closest to the second protruding fin. the method further includes etching the first plurality of protruding fins to form first recesses, growing first epitaxy regions from the first recesses, wherein the first epitaxy regions are merged to form a merged epitaxy region, etching the second protruding fin to form a second recess, and growing a second epitaxy region from the second recess. a top surface of the merged epitaxy region is lower on a side facing toward the second epitaxy region than on a side facing away from the second epitaxy region.
Inventor(s): Shao-Jyun Wu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Liang Pan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/28, H01L21/311, H01L21/321, H01L27/092
CPC Code(s): H01L21/823842
Abstract: a method of forming a semiconductor device includes forming a first dummy gate structure and a second dummy gate structure over a fin; forming a first dielectric layer around the first dummy gate structure and around the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure to form a first recess and a second recess in the first dielectric layer, respectively; forming a gate dielectric layer in the first recess and the second recess; forming a first work function layer over the gate dielectric layer in the first and the second recesses; removing the first work function layer from the first recess; converting a surface layer of the first work function layer in the second recess into an oxide; and forming a second work function layer in the first recess over the gate dielectric layer and in the second recess over the oxide.
Inventor(s): Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Jung Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tai-Min Chang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Wei Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L21/56, H01L23/00, H01L23/538, H01L25/065
CPC Code(s): H01L23/3114
Abstract: provided is a package structure including a first die and an encapsulant. the first die includes a substrate, a plurality of pads over the substrate, a passivation layer on portions of each of the plurality of pads, a plurality of first die connectors on the plurality of pads, respectively and a dielectric layer laterally encapsulating the plurality of first die connectors. the encapsulant laterally encapsulates the first die. one of the plurality of first die connectors is a taper-shaped die connector. a width of the one of the plurality of first die connectors gradually increases from a top surface of the one of the plurality of first die connectors toward the a top surface of the passivation layer.
Inventor(s): Chen-Hsiang Lao of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Sheng Chiu of Miaoli City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Chi Li of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chang Ku of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Shu Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/34, H01L23/40
CPC Code(s): H01L23/345
Abstract: a semiconductor package includes a first heat dissipation plate, a second heat dissipation plate, a plurality of heat generating assemblies, and a plurality of fixture components. the first heat dissipation plate has a first upper surface and a first lower surface. the first heat dissipation plate includes first through holes extended from the first upper surface to the first lower surface. the second heat dissipation plate has a second upper surface and a second lower surface. the second heat dissipation plate includes second through holes extended from the second upper surface to the second lower surface. the heat generating assemblies are disposed between the first heat dissipation plate and the second heat dissipation plate. the fixture components include fix screws and nuts. the fix screws penetrate through the first heat dissipation plate and the second heat dissipation plate along the first through holes and the second through holes.
Inventor(s): Chih-Chien Pan of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Wei Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Pu Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Hui Cheng of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/373, H01L23/00, H01L23/31, H01L23/498, H01L25/07, H01L29/68
CPC Code(s): H01L23/373
Abstract: a semiconductor package and a manufacturing method thereof are provided. the package includes a substrate, and first, second and third semiconductor elements disposed on and electrically connected to the substrate. a heat transfer enhancing layer, a thermal conductive material layer and an adhesive material layer are respectively disposed on and joined to the first, second and third semiconductor elements. a lid is disposed over the first, second and third semiconductor elements, and joined to the heat transfer enhancing layer, the thermal conductive material layer and the adhesive material layer. the thermal conductive material layer has a thermal conductivity lower than that of the heat transfer enhancing layer and higher than that of the adhesive material layer, and the thermal conductive material layer has a bonding strength larger than that of the heat transfer enhancing layer and smaller than that of the adhesive material layer.
Inventor(s): Kuan Yu Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yen Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin Yang Hung of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Lin of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng Tzeng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Yun Wu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-De Ho of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L21/8238, H01L27/092, H01L29/417, H01L29/66
CPC Code(s): H01L23/481
Abstract: a method includes forming a multi-layer stack comprising dummy layers and semiconductor layers located alternatingly, and forming a plurality of dummy gate stacks on sidewalls and a top surface of the multi-layer stack. two of the plurality of dummy gate stacks are immediately neighboring each other, and have a space in between. a first source/drain region and a second source/drain region are formed in the multi-layer stack, with the second source/drain region overlapping the first source/drain region. the method further includes replacing the plurality of dummy gate stacks with a plurality of replacement gate stacks, replacing a first one of the plurality of replacement gate stacks with a first dielectric isolation region, forming a deep contact plug in the space, forming a front-side via over the deep contact plug, and forming a back-side via under the deep contact plug, wherein the front-side via is electrically connected to the back-side via through the deep contact plug.
Inventor(s): Tzuan-Horng Liu of Longtan Township (TW) for taiwan semiconductor manufacturing company, ltd., An-Jhih Su of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yuan Yu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yuan Teng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Ming Weng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Che-Hsiang Hsu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L21/48, H01L21/60
CPC Code(s): H01L23/49827
Abstract: a method includes forming a first package component and a second package component. the first package component includes a first polymer layer, and a first electrical connector, with at least a part of the first electrical connector being in the first polymer layer. the second package component comprises a second polymer layer, and a second electrical connector, with at least a part of the second electrical connector being in the second polymer layer. the first package component is bonded to the second package component, with the first polymer layer being bonded to the second polymer layer, and the first electrical connector being bonded to the second electrical connector.
Inventor(s): Shu-Wei Li of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chen Chan of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Yi Yang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Han Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528
CPC Code(s): H01L23/5226
Abstract: in some embodiments, the present disclosure relates to a semiconductor structure. the semiconductor structure includes a substrate. a liner layer is arranged along a sidewall of the substrate within a cross-sectional view. a conductive 2d material is arranged on the liner layer within the cross-sectional view. the conductive 2d material includes a top surface that is above a top surface of the liner layer. a conductive structure continuously extends from above a top of the conductive 2d material to below a bottom of the conductive 2d material. the conductive 2d material and the liner layer laterally separate the substrate from the conductive structure.
Inventor(s): Cheng-Wei Chang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Li Wang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ying Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hung Chu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Fang-Wei Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/285, H01L21/768, H01L23/528, H01L23/532
CPC Code(s): H01L23/5226
Abstract: in some embodiments, the present disclosure relates to an integrated circuit device. a transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. a lower conductive plug is disposed through a lower inter-layer dielectric (ild) layer and contacting a first source/drain region. a capping layer is disposed directly on the lower conductive plug. an upper inter-layer dielectric (ild) layer is disposed over the capping layer and the lower ild layer. an upper conductive plug is disposed through the upper ild layer and directly on the capping layer.
Inventor(s): I-Che Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huai-Ying Huang of Jhonghe City (TW) for taiwan semiconductor manufacturing company, ltd., Ruei-Cheng Shiu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/768, H01L23/522, H01L23/532, H01L25/18
CPC Code(s): H01L23/5283
Abstract: a second metal structure such as a metal plug is formed over a first metal structure, such as a metal line, by causing metal material from the first metal structure to migrate into an opening in a dielectric layer over the first metal structure. the metal material, which may be copper, is of a type that undergoes a reduction in density as it oxidizes. migration is induced using gases that alternately oxidize and reduce the metal material. over many cycles, the metal material migrates into the opening. in some embodiments, the migrated metal material partially fills the opening. in some embodiments, the migrated metal material completely fills the opening.
Inventor(s): Chen-Hsuan Tsai of Taitung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Lin CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Chuan Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ching Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/56, H01L23/00, H01L23/31, H01L23/498, H01L25/10
CPC Code(s): H01L23/5386
Abstract: a package structure includes a first redistribution circuit structure, a first semiconductor die, and a second semiconductor die. the first redistribution circuit structure has a first side and a second side opposite to the first side. the first semiconductor die is disposed over the firs side of the first redistribution circuit structure. the second semiconductor die is disposed over the second side of the first redistribution circuit structure and is electrically connected thereto, where the second semiconductor die includes a substrate, an interconnect structure disposed on the substrate, a plurality of conductive terminals disposed on and electrically connected to the interconnect structure, and a dielectric layer disposed on the interconnect structure and laterally covering the plurality of conductive terminals. a material of the dielectric layer included in the second semiconductor die is different from a material of a dielectric layer included in the first redistribution circuit structure.
Inventor(s): Tsung-Yang Hsieh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Chang Lee of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Ping Lai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chung Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Kang Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Mei-Shih Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Ai Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L25/00, H01L25/065
CPC Code(s): H01L23/562
Abstract: a method is provided for forming an integrated circuit (ic) chip package structure. the method includes: providing an interposer having a front surface and a back surface, the interposer comprising a substrate, at least one routing region, and at least one non-routing region; forming at least one warpage-reducing trench in the at least one non-routing region, wherein the at least one warpage-reducing trench extends from the front surface of the interposer to a first depth, the first depth smaller than a thickness between the front surface and the back surface of the interposer; depositing a warpage-relief material in the at least one warpage-reducing trench; and bonding the group of ic dies to the front surface of the interposer.
Inventor(s): Chung-Shi Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jiun Yi Wu of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hsun Lee of Chu-tung Town (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L21/78, H01L23/31, H01L23/538, H01L25/00, H01L25/10
CPC Code(s): H01L23/562
Abstract: in an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a conductive via extending through the encapsulant; a redistribution structure on the encapsulant, the redistribution structure including: a metallization pattern electrically coupled to the conductive via and the integrated circuit die; a dielectric layer on the metallization pattern, the dielectric layer having a first thickness of 10 �m to 30 �m; and a first under-bump metallurgy (ubm) having a first via portion extending through the dielectric layer and a first bump portion on the dielectric layer, the first ubm being physically and electrically coupled to the metallization pattern, the first via portion having a first width, a ratio of the first thickness to the first width being from 1.33 to 1.66.
Inventor(s): Tsung-Yuan Yu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tzuan-Horng Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Liang Lin of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/58, H01L21/48, H01L21/56, H01L23/31, H01L23/498, H01L23/538, H01L25/10
CPC Code(s): H01L23/585
Abstract: a package structure includes a first package. the first package has an active region and a peripheral region surrounding the active region. the first package includes a first redistribution structure, a second redistribution structure, a die, an encapsulant, and a seal ring structure. the second redistribution structure is disposed over the first redistribution structure. the die is disposed in the active region and is located between the first redistribution structure and the second redistribution structure. the encapsulant laterally encapsulates the die. the seal ring structure is disposed in the peripheral region. a first portion of the seal ring structure is embedded in the first redistribution structure, and a second portion of the seal ring structure is embedded in the second redistribution structure.
Inventor(s): Ming-Hong Chang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yi Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kun-Ming Huang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Tao Chu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shen-Ping Wang of Keelung City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Li Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L23/29, H01L23/31, H01L23/50, H01L23/522, H01L23/528
CPC Code(s): H01L24/05
Abstract: an integrated circuit (ic) comprising an enhanced passivation scheme for pad openings and trenches is provided. in some embodiments, an interlayer dielectric (ild) layer covers a substrate and at least partially defines a trench. the trench extends through the ild layer from a top of the ild layer to the substrate. a conductive pad overlies the ild layer. a first passivation layer overlies the ild layer and the conductive pad, and further defines a pad opening overlying the conductive pad. a second passivation layer overlies the ild layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ild layer in the trench. further, the second passivation layer has a low permeability for moisture or vapor relative to the ild layer.
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jie Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L25/00, H01L25/065
CPC Code(s): H01L24/08
Abstract: a semiconductor package includes a first semiconductor die, a second semiconductor die and a plurality of bumps. the first semiconductor die has a front side and a backside opposite to each other. the second semiconductor die is disposed at the backside of the first semiconductor die and electrically connected to first semiconductor die. the plurality of bumps is disposed at the front side of the first semiconductor die and physically connects first die pads of the first semiconductor die. a total width of the first semiconductor die may be less than a total width of the second semiconductor die.
Inventor(s): Ying-Ju Chen of Tuku Township (TW) for taiwan semiconductor manufacturing company, ltd., An-Jhih Su of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Der-Chyang Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hsi Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L25/10
CPC Code(s): H01L24/32
Abstract: a method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. the first device comprises an integrated passive device (ipd) and a first contact pad disposed over the ipd. the second device comprises a second contact pad. the first contact pad has a first surface with first lateral extents. the second contact pad has a second surface with second lateral extents. the width of the second lateral extents is less than the width of the first lateral extents. the joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. the solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. at least one of the first surface or the second surface is substantially planar.
Inventor(s): Zheng Yong Liang of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Ting Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jyh-Cherng Sheu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Yun Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Chu Lin of Ping-Tung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/18, H01L21/02, H01L21/768, H01L23/522
CPC Code(s): H01L25/18
Abstract: a carrier structure and methods of forming and using the same are described. in some embodiments, the method includes forming one or more devices over a substrate, forming a first interconnect structure over the one or more devices, and bonding the first interconnect structure to a carrier structure. the carrier structure includes a semiconductor substrate, a release layer, and a first dielectric layer, and the release layer includes a metal nitride. the method further includes flipping over the one or more devices so the carrier structure is located at a bottom, performing backside processes, flipping over the one or more devices so the carrier structure is located at a top, and exposing the carrier structure to ir lights. portions of the release layer are separated from the first dielectric layer.
Inventor(s): Chia-Jung Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Cheng Hsu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234, H10B61/00
CPC Code(s): H01L27/088
Abstract: a memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. the word lines are intersected with the bit lines. the auxiliary lines are disposed between the word lines and the of bit lines. the selectors are inserted between the bit lines and the auxiliary lines. the memory cells are inserted between the word lines and the auxiliary lines.
Inventor(s): Cheng-Ting Chung of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jin Cai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/822, H01L21/8238
CPC Code(s): H01L27/0922
Abstract: a method includes forming a complementary field-effect transistor (cfet) including a first finfet and a second finfet. the processes for forming the first finfet includes forming at least one semiconductor fin having a first total count, and forming a first gate stack on the at least one semiconductor fin. the second finfet is vertically aligned to the first finfet. the processes for forming the second finfet includes forming a plurality of semiconductor fins, wherein the plurality of semiconductor fins have a second total count greater than the first total count, and forming a second gate stack on the plurality of semiconductor fins.
Inventor(s): Seiji Takahashi of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jhy-Jyi Sze of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Hsiang Chen of Xihu Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, H01L21/02
CPC Code(s): H01L27/1463
Abstract: the present disclosure relates to a cmos image sensor. the image sensor comprises a pixel region comprising a photodiode disposed within a substrate. a deep trench isolation (dti) ring encloses the photodiode from top view and extends from a back-side to a first position within the substrate from cross-sectional view. a pair of shallow trench isolation (sti) structures is respectively disposed at an inner periphery and an outer periphery sandwiching the dti ring from top view and extends from a front-side to a second position within the substrate from cross-sectional view. a pixel device is disposed at the front-side of the substrate directly overlying the dti ring. the pixel device comprises a gate electrode disposed over the substrate and a pair of source/drain (s/d) regions disposed within the substrate and reaching on a top surface of the dti ring.
Inventor(s): Chih-Kuan Yu of Nantou County (TW) for taiwan semiconductor manufacturing company, ltd., U-Ting Chiu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shen-Hui Hong of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Chi Hung of Chu-Bei City (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, H04N25/79
CPC Code(s): H01L27/14643
Abstract: various embodiments of the present disclosure are directed towards an image sensor including a first chip stacked with a second chip. the first chip comprises a first substrate and a photodetector disposed in the first substrate. a first transistor is disposed on the first substrate and neighbors the photodetector. a plurality of second transistors is disposed within or on the stacked first and second chips. the plurality of second transistors comprises a first readout transistor having a first readout gate electrode over a first readout gate dielectric structure. the first readout gate dielectric structure comprises a lower dielectric layer stacked with an upper dielectric structure. a relative permittivity of the upper dielectric structure is greater than a relative permittivity of the lower dielectric layer.
Inventor(s): Guanyu Luo of Chiayi County (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Liang Cheng of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chau Chen of Tainan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/00, H01L23/522
CPC Code(s): H01L28/24
Abstract: a thin film resistor (tfr) is provided. the thin film resistor includes: a first insulator layer; a silicon chromium (sicr) thin film disposed on the first insulator layer, an oxidation prevention layer disposed on the sicr thin film; and a first contact structure and a second contact structure disposed on the oxidation prevention layer. the oxidation prevention layer is operable to prevent the sicr thin film from being oxidized during a wet etching process.
Inventor(s): Kuan-Kan Hu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Han-De Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ku-Feng Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Fong Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L25/07, H01L27/092, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0653
Abstract: bonding and isolation techniques for stacked device structures are disclosed herein. an exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. the bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. the isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. the method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. the first insulation layer and the second insulation layer may include the same or different materials.
Inventor(s): Kuan-Kan Hu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Han-De Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ku-Feng Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Fong Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L25/07, H01L27/092, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0653
Abstract: bonding and isolation techniques for stacked device structures are disclosed herein. an exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. the bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. the isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. the method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. the first insulation layer and the second insulation layer may include the same or different materials.
Inventor(s): Hsin-Yi Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Weng Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L27/092, H01L29/66, H01L29/78
CPC Code(s): H01L29/0673
Abstract: a semiconductor device includes: a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions, the gate structure including: a gate dielectric material around each of the nanosheets; a work function material around the gate dielectric material; a liner material around the work function material, where the liner material has a non-uniform thickness and is thicker at a first location between the nanosheets than at a second location along sidewalls of the nanosheets; and a gate electrode material around at least portions of the liner material.
Inventor(s): Winnie Victoria Wei-Ning Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0847
Abstract: semiconductor structures and processes of forming the same are provided. a semiconductor structure according to the present disclosure includes a substrate, a first source/drain feature disposed on the substrate, a first contact etch stop layer disposed on the first source/drain feature, a first dielectric layer disposed over the first cesl, an etch stop layer (esl) disposed on and in contact with the first cesl and the first dielectric layer, a second source/drain feature disposed over the esl, a second (cesl) disposed on the second source/drain feature, a second dielectric layer disposed over the second cesl. the first source/drain feature includes silicon and an n-type dopant and the second source/drain feature includes silicon germanium and a p-type dopant.
Inventor(s): Cheng-Yi PENG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ting TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Wei HUNG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Ting CHEN of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Hua LAI of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Song-Bor LEE of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Bor-Zen TIEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L21/02, H01L21/265, H01L29/24, H01L29/78
CPC Code(s): H01L29/0847
Abstract: a semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. the source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of sias.
Inventor(s): Kuan-Hsun Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Chieh Hsiao of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chih Hsin Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Wei Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/768, H01L23/48, H01L29/06, H01L29/786
CPC Code(s): H01L29/42392
Abstract: a first conductive pad disposed over a first side of a substrate in a first direction. a second conductive pad is disposed over a second side of the substrate in the first direction. a through-substrate via (tsv) extends into the substrate in the first direction. the tsv is disposed between the first conductive pad and the second conductive pad in the first direction. an air liner disposed between the tsv and the substrate in a second direction different from the first direction.
Inventor(s): Jung-Hung CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Han CHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Cheng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Cheng CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Cheng TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8238, H01L27/092, H01L29/06, H01L29/08, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/42392
Abstract: a device includes: a stack of nanostructures; a gate structure that wraps around the nanostructures; an isolation region between the stack of nanostructures and another stack of nanostructures adjacent thereto along a first direction; a source/drain region that abuts at least one of the nanostructures; and a spacer layer that is on sidewalls of the gate structure and on sidewalls of the source/drain region, the spacer layer covering an area between the source/drain region and a neighboring source/drain region of another transistor along the first direction.
Inventor(s): Chi-Yi CHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei TSAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/51, H01L27/092, H01L29/66, H01L29/78
CPC Code(s): H01L29/516
Abstract: the present disclosure relates to a hybrid integrated circuit. in one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. moreover, the integrated circuit may have a second region with a second gate structure having a high-� gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. the integrated circuit may further have at least one trench isolation between the first region and the second region.
Inventor(s): Chung-Liang CHENG of Changhua County 500 (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Tsung Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Haung-Lin Chao of Hillsboro OR (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/8234, H01L23/48, H01L29/08, H01L29/66
CPC Code(s): H01L29/7851
Abstract: a semiconductor device and methods of fabricating the same are disclosed. the semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (s/d) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the s/d region. the gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. the gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. the semiconductor device further includes a first contact structure disposed within the gate capping structure and a first via structure disposed on the first contact structure.
20240283416. AMPLIFIER SYSTEM_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Kunal Mahaseth of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsieh-Hung Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03F3/195, H03F1/56
CPC Code(s): H03F3/195
Abstract: an amplifier system includes an input pad having an input shunt capacitance, an output pad having an output shunt capacitance, and a high frequency amplifier including an input terminal coupled to the input pad and an output terminal coupled to the output pad. the input shunt capacitance is greater than the output shunt capacitance.
Inventor(s): Hsin-Cheng LIN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tao CHOU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chee-Wee LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/125
Abstract: a memory device includes a first pull-down transistor, a first pass-gate transistor, a second pull-down transistor, a second pass-gate transistor, a first pull-up transistor, and a second pull-up transistor. a first power line, a first bit line, and a second bit line is provided, the first power line includes first and second portions separated from each other, wherein in a cross-sectional view, the second portion of the first power line is laterally between the first and second bit lines along a direction. a first via electrically connects the first portion of the first power line to the first pull-down transistor. a second via electrically connects the first bit line to the first pass-gate transistor. a third via electrically connects the second portion of the first power line to the second pull-down transistor. a fourth via electrically connects the second bit line to the second pass-gate transistor.
Inventor(s): Yen-Lin CHUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kao-Cheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei Min CHAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Huei CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/125
Abstract: a static random access memory (sram) includes: first and second cfet stacks, each of which includes a first active region (ar), e.g., n-type, stacked in a first direction on a second ar (e.g., p-type), each cfet stack representing a complementary fet (cfet) architecture; an upper half of a third cfet stack; a lower half of a fourth cfet stack; the first and second cfet stacks including fets that comprise a latch of the sram; the first cfet stack further including fets that comprise first and third ports of the sram; the second cfet stack further including fets that comprise second and fourth ports of the sram; the lower half of the fourth cfet stack including fets that comprise a fifth port of the sram; and the upper half of the third cfet stack including fets that comprise a sixth port of the sram.
Inventor(s): Feng-Cheng Yang of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Han-Jong Chia of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chen Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/20, G11C5/06, G11C11/22, H01L21/822, H01L29/66, H01L29/78
CPC Code(s): H10B51/20
Abstract: a semiconductor device and method of manufacture are provided. in embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.
Inventor(s): Hengyuan Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Xinyu BAO of Fremont CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B63/00
CPC Code(s): H10B63/34
Abstract: a semiconductor device includes a first conductive line, a second conductive line, a third conductive line, a first semiconductor layer, a memory layer and a conductive layer. the first conductive line and the second conductive line extend along a first direction. the third conductive line extends along a second direction substantially perpendicular to the first direction. the first semiconductor layer extends along the second direction to surround the third conductive line. the memory layer is disposed between the first semiconductor layer and the second conductive line. the conductive layer is disposed between the memory layer and the first semiconductor layer.
Inventor(s): Timothy VASEN of Linthicum Heights MD (US) for taiwan semiconductor manufacturing company, ltd., Mark VAN DAL of Linden (BE) for taiwan semiconductor manufacturing company, ltd., Gerben DOORNBOS of Kessel-Lo (BE) for taiwan semiconductor manufacturing company, ltd., Matthias PASSLACK of Hayward CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10K10/46, H10K19/10, H10K85/20
CPC Code(s): H10K10/484
Abstract: in a method of forming a gate-all-around field effect transistor (gaa fet), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (cnts) are disposed over the bottom support layer. a first support layer is formed over the first group of cnts and the bottom support layer such that the first group of cnts are embedded in the first support layer. a second group of carbon nanotubes (cnts) are disposed over the first support layer. a second support layer is formed over the second group of cnts and the first support layer such that the second group of cnts are embedded in the second support layer. a fin structure is formed by patterning at least the first support layer and the second support layer.
Inventor(s): Huan-Chieh Chen of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Wen Chang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/20, H10N70/00
CPC Code(s): H10N70/231
Abstract: a phase-change material (pcm) switching device includes: a base dielectric layer; a spreader element disposed in the base dielectric layer, wherein the spreader element extends in a first horizontal direction and comprises: a central portion extending in the first horizontal direction and having a first width in a second horizontal direction perpendicular to the first horizontal direction; a first end portion at a first end of the central portion and having a second width in the second horizontal direction; and a second end portion at a second end of the central portion and having a third width in the second horizontal direction, and wherein at least one of the second width and the third width is larger than the first width; a heater element disposed over the spreader element; a thermal barrier element disposed on the heater element; and a pcm layer disposed on the thermal barrier element.
Inventor(s): Yu-Chao Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Sheng Chen of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Carlos H. Diaz of Los Altos Hills CA (US) for taiwan semiconductor manufacturing company, ltd., Da-Ching Chiou of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/20, H01L23/528, H10B63/00, H10N70/00
CPC Code(s): H10N70/231
Abstract: a memory cell includes a bottom electrode, a storage element layer, a first buffer layer, and a top electrode. the storage element layer is disposed over the bottom electrode. the first buffer layer is interposed between the storage element layer and the bottom electrode, where a thermal conductivity of the first buffer layer is less than a thermal conductivity of the storage element layer. the top electrode is disposed over the storage element layer, where the storage element layer is disposed between the top electrode and the first buffer layer.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on August 22nd, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- B08B9/032
- B08B13/00
- CPC B08B9/0321
- Taiwan semiconductor manufacturing company, ltd.
- G02B6/13
- CPC G02B6/131
- G02B6/42
- CPC G02B6/4206
- G02B6/293
- CPC G02B6/4215
- CPC G02B6/4283
- G03F1/64
- G03F1/22
- CPC G03F1/64
- G03F7/039
- B82Y30/00
- B82Y40/00
- G03F7/004
- G03F7/038
- G03F7/20
- G03F7/30
- G03F7/32
- G03F7/36
- G03F7/38
- G03F7/40
- CPC G03F7/0397
- G03F7/00
- CPC G03F7/70341
- G11C7/10
- G06F7/501
- G06F7/544
- G11C7/12
- CPC G11C7/1069
- G11C11/412
- G11C11/419
- H03K19/20
- H10B10/00
- CPC G11C11/412
- H01J27/08
- H01J27/02
- H01J37/317
- H01L21/26
- CPC H01J27/08
- H01L21/02
- H01L21/768
- H01L21/8238
- H01L23/532
- H01L27/092
- H01L29/08
- H01L29/40
- H01L29/66
- H01L29/775
- CPC H01L21/02068
- C23C14/06
- C23C14/08
- C23C14/22
- C23C16/02
- C23C16/04
- C23C16/30
- C23C16/40
- C23C16/455
- H01J37/32
- H01L21/033
- H01L21/308
- H01L21/311
- H01L23/528
- CPC H01L21/02126
- H01L21/027
- G03F7/09
- G03F7/095
- H01L21/306
- CPC H01L21/0273
- CPC H01L21/0274
- H01L21/266
- H01L21/66
- H01L27/146
- CPC H01L21/3086
- H01L21/477
- H01L21/475
- H01L21/4757
- H01L27/088
- CPC H01L21/477
- H01L21/48
- H01L23/00
- H01L23/498
- CPC H01L21/4857
- H01L21/677
- B65G47/90
- H01L21/673
- CPC H01L21/67772
- CPC H01L21/7682
- H01L23/522
- CPC H01L21/76843
- CPC H01L21/76861
- H01L21/8234
- CPC H01L21/76871
- CPC H01L21/76873
- CPC H01L21/76877
- H01L21/3213
- H01L21/56
- H01L29/06
- CPC H01L21/823481
- H01L21/762
- H01L29/423
- H01L29/78
- H01L29/786
- H01L21/285
- H01L29/417
- H01L29/45
- CPC H01L21/823814
- H01L21/28
- H01L21/321
- CPC H01L21/823842
- H01L23/31
- H01L23/538
- H01L25/065
- CPC H01L23/3114
- H01L23/34
- H01L23/40
- CPC H01L23/345
- H01L23/373
- H01L25/07
- H01L29/68
- CPC H01L23/373
- H01L23/48
- CPC H01L23/481
- H01L21/60
- CPC H01L23/49827
- CPC H01L23/5226
- H01L25/18
- CPC H01L23/5283
- H01L25/10
- CPC H01L23/5386
- H01L25/00
- CPC H01L23/562
- H01L21/78
- H01L23/58
- CPC H01L23/585
- H01L23/29
- H01L23/50
- CPC H01L24/05
- CPC H01L24/08
- CPC H01L24/32
- CPC H01L25/18
- H10B61/00
- CPC H01L27/088
- H01L21/822
- CPC H01L27/0922
- CPC H01L27/1463
- H04N25/79
- CPC H01L27/14643
- H01L29/00
- CPC H01L28/24
- CPC H01L29/0653
- CPC H01L29/0673
- CPC H01L29/0847
- H01L21/265
- H01L29/24
- CPC H01L29/42392
- H01L29/51
- CPC H01L29/516
- CPC H01L29/7851
- H03F3/195
- H03F1/56
- CPC H03F3/195
- CPC H10B10/125
- H10B51/20
- G11C5/06
- G11C11/22
- CPC H10B51/20
- H10B63/00
- CPC H10B63/34
- H10K10/46
- H10K19/10
- H10K85/20
- CPC H10K10/484
- H10N70/20
- H10N70/00
- CPC H10N70/231
