Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on May 16th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd. on May 16th, 2024
Taiwan Semiconductor Manufacturing Co., Ltd.: 51 patent applications
Taiwan Semiconductor Manufacturing Co., Ltd. has applied for patents in the areas of H01L29/66 (12), H01L27/088 (10), H01L29/775 (10), H01L29/06 (9), H01L29/423 (9)
With keywords such as: layer, structure, semiconductor, dielectric, gate, metal, conductive, device, top, and die in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s): Szu-Chen HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Po-Hsien CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Mao-Jung CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Mao-Shun LIEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Fu-Hsien LI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): B31B50/00, B31B50/02, B31B50/07, B31B50/52
Abstract: an apparatus and method for expanding a box blank into a box, the apparatus comprising an arm assembly, a controller, a camera and a box blank conveyor. the arm assembly includes a folding arm having a position in a first direction and a rotational angle controlled by the controller based on a position of a feature of the box blank in the field of view of the camera. the camera captures images of the box blank which are used to position the arm assembly and to evaluate the need to reject a box blank.
Inventor(s): Po-Zeng KANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Shen CHOU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Chow PENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G01K7/01, H01L23/522, H01L27/092, H01L29/78
Abstract: a semiconductor device includes a plurality of active area structures extending in parallel, first and second dummy gate layers spanning the plurality of active area structures, a first active device including first portions of the plurality of active area structures between the first and second dummy gate layers, a metal layer spanning the plurality of active area structures between the first and second dummy gate layers, and a pair of vias positioned at opposite ends of the metal layer. a first via of the pair of vias is configured to be electrically connected to ground, and a second via of the pair of vias is configured to be electrically connected to a current source and a circuit configured to measure a voltage at the node.
Inventor(s): Huan-Neng CHEN of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Chewn-Pu JOU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Lan-Chou CHO of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Wei KUO of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G02F1/225, G02F1/017, G02F1/025
Abstract: in an embodiment, a phase shifter includes: a light input end; a light output end; a p-type semiconductor material, and an n-type semiconductor material contacting the p-type semiconductor material along a boundary area, wherein the boundary area is greater than a length from the light input end to the light output end multiplied by a core width of the phase shifter.
Inventor(s): Chi-Hung LIAO of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yueh-Lin YANG of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F7/00, G03F7/20, H01L21/027, H05G2/00
Abstract: a lithography method in semiconductor fabrication is provided. the method includes generating a plurality of first drops of a target material through a first nozzle group selected from a plurality of nozzles to form a first elongated droplet; generating a first laser pulse to convert the first elongated droplet into plasma that generates a first extreme ultraviolet (euv) radiation; reflecting the first euv radiation by a collector mirror having an optical axis; generating a plurality of second drops of the target material through a second nozzle group selected from the plurality of nozzles to form a second elongated droplet, the second elongated droplet being oblique with the optical axis of the collector mirror at a different angle than the first elongated droplet.
Inventor(s): Chao-Chun Lo of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Boh-Yi Huang of San Jose CA (US) for taiwan semiconductor manufacturing co., ltd., Chih-yuan Stephen Yu of San Jose CA (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/33
Abstract: systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (asic) and system on chip (soc) designs. a target circuit design having a first set of netlists and timing constraints is received. a plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. the clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (sta). the attribute mismatch is provided for further design or timing constraint modifications and/or updates using this approach, particularly timing formal verification, at the target technology in order to enable efficient design timing sign-off based on ported netlists and synthesis design constraints (sdc).
Inventor(s): Sheng-Hsiung Chen of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Huang-Yu Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Hsing Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jerry Chang Jui Kao of Taipei (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/3947, G06F30/39
Abstract: the routing of conductors in the conductor layers in an integrated circuit are routed using mixed-manhattan-diagonal routing. various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-manhattan-diagonal routing.
Inventor(s): Ke-Ying SU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jon-Hsu HO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ke-Wei SU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Liang-Yi CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Hsing HSIEH of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Koi LAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Keng-Hua KUO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., KuoPei LU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Lester CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ze-Ming WU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06F30/398, G03F1/36, G03F1/70, G06F30/20
Abstract: a method of generating an ic layout diagram includes receiving an ic layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the ic layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the ic layout diagram.
20240161787.Memory Device_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Chien-Chen Lin of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Wei Min Chan of Taipei County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C5/14, G11C7/12, G11C7/22, G11C8/08
Abstract: a method of operating a memory device is provided. a clock signal is received. each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. a power nap period is then determined. the power nap period is compared with a clock cycle period to determine that the power nap period is less than the clock cycle period of the clock signal. a header control signal is generated in response to determining that the power nap period is less than the clock cycle period. the header control signal turns off a header of a component of the memory device.
Inventor(s): Bo-Feng YOUNG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ming LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Lien Linus LU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Han-Jong CHIA of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sai-Hooi YEONG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-En HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yih WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C7/12, G06F30/39, G11C8/08
Abstract: an integrated circuit (ic) device includes memory cells each including first through fourth memory elements. the first memory element is physically arranged, along a first axis, between a bit line and a first auxiliary conductive line. the second memory element is physically arranged, along the first axis, between a second auxiliary conductive line and a first conductor. the first and second memory elements are arranged in a first row along the first axis. the third memory element is physically arranged, along the first axis, between the first auxiliary conductive line and a second conductor electrically coupled to the first conductor. the fourth memory element is physically arranged, along the first axis, between the bit line and the second auxiliary conductive line. the third and fourth memory elements are arranged, along the first axis, in a second row spaced from the first row along an axis transverse to the first axis.
Inventor(s): Xiu-Li YANG of Shanghai City (CN) for taiwan semiconductor manufacturing co., ltd., He-Zhou WAN of Shanghai City (CN) for taiwan semiconductor manufacturing co., ltd., Mu-Yang YE of Nanjing City (CN) for taiwan semiconductor manufacturing co., ltd., Lu-Ping KONG of Nanjing City (CN) for taiwan semiconductor manufacturing co., ltd., Ming-Hung CHANG of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C7/12, G11C7/10, G11C7/22
Abstract: a device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. the memory array has bit cells arranged in rows and columns. each bit line pair is connected to a respective column of bit cells. each word line is connected to a respective row of bit cells. the modulation circuit is coupled with at least one bit line pair. the control signal generator is coupled with the modulation circuit. the control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. the control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. a method of controlling aforesaid device is also disclosed.
Inventor(s): Katherine H. CHIANG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Te LIN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C11/22, H10B51/20, H10B51/30
Abstract: a memory system including a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a plurality of source lines. the plurality of memory cells are arranged in rows and columns, each of the plurality of memory cells having a gate, a drain, and a source. in the plurality of word lines, each of the word lines having a corresponding row, wherein each of the word lines is coupled to the gates of the memory cells in the corresponding row. in the plurality of bit lines and the plurality of source lines, each of the bit lines and each of the source lines having a corresponding column, where each of the bit lines is connected to the drain of the memory cells in the corresponding column and each of the source lines is connected to the source of the memory cells in the corresponding column. where, in a write operation, the word line corresponding to a selected memory cell is configured to receive a first voltage, and the bit line and the source line of the selected memory cell are configured to receive a second voltage, and where one of the first voltage or the second voltage is a positive voltage and the other of the first voltage or the second voltage is a negative voltage.
Inventor(s): Jhon Jhy LIAW of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C11/412, H01L23/48, H01L23/528, H10B10/00
Abstract: embodiments of the present disclosure relate to a memory bit cell including two doped regions and four gate structures. bit line, bit line bar, and word line of the bit cell are formed on a front side of the bit cell and power rails are formed on a back side of the bit cell. in some embodiments, each bit cell includes two word lines.
Inventor(s): Wei-jer Hsieh of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Hao Hsu of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Zhi-Hao Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng Hung Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C11/419
Abstract: a memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first wl pulse having a rising edge and a falling edge that define a pulse width of the first wl pulse; a first tracking wl, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (bl) configured to write a logic state to the memory cell, a second wl pulse having a rising edge with a decreased slope; and a first tracking bl, configured to emulate the bl, that is coupled to the first tracking wl such that the pulse width of the first wl pulse is increased based on the decreased slope of the rising edge of the second wl pulse.
Inventor(s): Cheng-Hsien Chou of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Lung Lin of Taichung (TW) for taiwan semiconductor manufacturing co., ltd., Chun Liang Chen of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Liang Liu of Pingtung County (TW) for taiwan semiconductor manufacturing co., ltd., Chin-Yu Ku of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jong-Yuh Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01J37/147, H01J37/317
Abstract: a deflecting plate includes a silicon-on-insulator (soi) substrate. the soi substrate includes: an insulator layer having a top surface and a bottom surface; a device layer coupled to the insulator layer at the top surface, wherein multiple deflecting apertures are disposed in the device layer, each of which extending from a top open end to a bottom open end through the device layer, and wherein the bottom open end is coplanar with the top surface of the insulator layer; and a handle substrate coupled to the insulator layer at the bottom surface, wherein a cavity is disposed in the handle substrate and extends from a cavity open end to a cavity bottom wall, and wherein the bottom wall is coplanar with the top surface of the insulator layer, such that the bottom open end of each deflecting aperture is exposed to the cavity.
Inventor(s): Kuo-Ming WU of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Hau-Yi HSIAO of Chiayi City (TW) for taiwan semiconductor manufacturing co., ltd., Kai-Yun YANG of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Che Wei YANG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Chau CHEN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Yi YU of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Yuan TSAI of Chu-Pei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/56
Abstract: some implementations described herein include systems and techniques for fabricating a stacked die product. the systems and techniques include using a supporting fill mixture that includes a combination of types of composite particulates in a lateral gap region of a stack of semiconductor substrates and along a perimeter region of the stack of semiconductor substrates. one type of composite particulate included in the combination may be a relatively smaller size and include a smooth surface, allowing the composite particulate to ingress deep into the lateral gap region. properties of the supporting fill mixture including the combination of types of composite particulates may control thermally induced stresses during downstream manufacturing to reduce a likelihood of defects in the supporting fill mixture and/or the stack of semiconductor substrates.
Inventor(s): Jhon Jhy Liaw of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/67, H01L21/033, H01L21/04
Abstract: semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (gaa) transistor structures and manufacturing methods thereof. different thickness in an epi-growth scheme is adopted to create different sheet thicknesses within the same device channel regions for use in manufacturing vertically stacked nanostructure (e.g., nanosheet, nanowire, or the like) gaa devices. a gaa device may be formed with a vertical stack of nanostructures in a channel region with a topmost nanostructure of the vertical stack being thicker than the other nanostructures of the vertical stack. furthermore, an ldd portion of the topmost nanostructure may be formed as the thickest of the nanostructures in the vertical stack.
Inventor(s): Chih-Hung HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Lung WU of Zhunan Township (TW) for taiwan semiconductor manufacturing co., ltd., Zheng-Lin HE of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yang-Ann CHU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jiun-Rong PAI of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Hsuan LEE of Tainan (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/67, B07C5/34, G01R31/01, H01L21/677
Abstract: a die sorter tool may include a first conveyor, and a first lane to receive, from one or more load ports and via the first conveyor, a carrier with a set of dies. the die sorter tool may include a die flip module to receive the carrier from the first lane, manipulate one or more dies of the set of dies by changing orientations of the one or more dies, and return the one or more dies to the carrier after manipulating the one or more dies and without changing positions of the one or more dies within the carrier. the die sorter tool may include a second conveyor, and a second lane to receive, via the second conveyor, the carrier from the die flip module, and provide, via the first conveyor, the carrier to the one or more load ports.
Inventor(s): Chih-Hung HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Lung WU of Zhunan Township (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Fam SHIU of Toufen City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Chen CHEN of Hemei Township (TW) for taiwan semiconductor manufacturing co., ltd., Yang-Ann CHU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jiun-Rong PAI of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/677, B23Q15/00, B23Q16/00, G05D5/04, H01L23/04
Abstract: a multiple die container load port may include a housing with an opening, and an elevator to accommodate a plurality of different sized die containers. the multiple die container load port may include a stage supported by the housing and moveable within the opening of the housing by the elevator. the stage may include one or more positioning mechanisms to facilitate positioning of the plurality of different sized die containers on the stage, and may include different portions movable by the elevator to accommodate the plurality of different sized die containers. the multiple die container load port may include a position sensor to identify one of the plurality of different sized die containers positioned on the stage.
Inventor(s): Shuen-Shin LIANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Han WANG of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Keng-Chu LIN of Chao-Chou Ping-Tung (TW) for taiwan semiconductor manufacturing co., ltd., Tetsuji UENO of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ting-Ting CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L29/66
Abstract: the present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. the first and second sidewalls oppose each other. the method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. the second dielectric material and the first and second sidewalls entrap a pocket of air. the method also includes performing a treatment process on the second dielectric material.
Inventor(s): Hsin-Yen HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ting-Ya LO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shao-Kuan LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Lin TENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Chin LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsiao-Kang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768
Abstract: a method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.
Inventor(s): Hsia-Wei CHEN of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Fu-Ting SUNG of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Wen LIAO of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Ting CHU of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Fa-Shen JIANG of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Tzu-Hsuan YEH of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/528, H01L23/532
Abstract: an integrated circuit device includes an interconnect layer, a memory structure, a third conductive feature, and a fourth conductive feature. the interconnect layer includes a first conductive feature and a second conductive feature. the memory structure is over and in contact with the first conductive feature. the memory structure includes at least a resistance switching element over the first conductive feature. the third conductive feature, including a first conductive line, is over and in contact with the second conductive feature. the fourth conductive feature is over and in contact with the memory structure. the fourth conductive feature includes a second conductive line, a top surface of the first conductive line is substantially level with a top surface of the second conductive line, and a bottom surface of the first conductive line is lower than a bottommost portion of a bottom surface of the second conductive line.
Inventor(s): Shih-Chuan CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jia-Chuan YOU of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Hao CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Yuan CHEN of HsinChu (TW) for taiwan semiconductor manufacturing co., ltd., Tien-Lu LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ming LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Baoshan Township, Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L21/768, H01L23/522, H01L27/088, H01L29/06, H01L29/66, H01L29/78
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. the electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. the first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.
Inventor(s): Kuan-Da Huang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Hao-Heng Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Li-Te Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L27/02, H01L27/088
Abstract: in some embodiments, the present disclosure relates to an integrated chip including a gate electrode over a substrate. a pair of source/drain regions are disposed in the substrate on opposing sides of the gate electrode. a dielectric layer is over the substrate. an etch stop layer is between the gate electrode and the dielectric layer. a gate capping layer overlies the gate electrode, continuously extends from a top surface of the etch stop layer to a top surface of the gate electrode, and comprises a curved sidewall over the top surface of the etch stop layer. a conductive contact overlies an individual source/drain region. a width of the conductive contact continuously decreases from a top surface of the conductive contact to a first point disposed above a lower surface of the gate capping layer. the conductive contact extends along the curved sidewall of the gate capping layer.
Inventor(s): Hung-Yi Kuo of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Chung Yee of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Jen Lien of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Ke-Han Shen of Chiayi City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Kong Sheng of Chu-Nan (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Shi Liu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Szu-Wei Lu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Fu Tsai of Changhua City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Ju Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Ming Ke of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/367, H01L21/56, H01L23/00, H01L23/31, H01L23/373, H10B80/00
Abstract: in an embodiment, a package includes an integrated circuit device attached to a substrate; an encapsulant disposed over the substrate and laterally around the integrated circuit device, wherein a top surface of the encapsulant is coplanar with the top surface of the integrated circuit device; and a heat dissipation structure disposed over the integrated circuit device and the encapsulant, wherein the heat dissipation structure includes a spreading layer disposed over the encapsulant and the integrated circuit device, wherein the spreading layer includes a plurality of islands, wherein at least a portion of the islands are arranged as lines extending in a first direction in a plan view; a plurality of pillars disposed over the islands of the spreading layer; and nanostructures disposed over the pillars.
Inventor(s): Ching-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ting-Chu Ko of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Der-Chyang Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/48, H01L21/311, H01L21/66, H01L21/768, H01L23/00
Abstract: an embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure including dielectric layers and metallization patterns therein, the metallization patterns including a top metal layer including top metal structures, forming a passivation layer over the top metal structures of the first interconnect structure, forming a first opening through the passivation layer, forming a probe pad in the first opening and over the passivation layer, the probe pad being electrically connected to the first top metal structure, performing a circuit probe test on the probe pad, removing the probe pad, and forming a bond pad and a bond via in dielectric layers over the passivation layer, the bond pad and bond via being electrically coupled to a second top metal structure of the top metal structures and a third top metal structure of the top metal structures.
Inventor(s): Shih-Wei PENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Min HSIAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Hsu CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jiann-Tyng TZENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, G03F1/42, G06F30/392, G06F30/394
Abstract: a method of manufacturing a plurality of via structures includes providing an integrated circuit (ic) photo mask including via features and assist features positioned exclusively along alternating diagonal grid lines of a grid, aligning the ic photo mask with first metal segments of a first metal layer of a semiconductor substrate, the first metal segments having a first spacing corresponding to a first pitch of the grid, performing one or more photolithography processes including the ic photo mask, thereby defining via structure locations corresponding to the via features, and forming via structures at the defined via structure locations.
20240162145.RESISTOR WITHIN A VIA_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Chi-Han YANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L21/321, H01L21/768, H01L23/532
Abstract: in some implementations, one or more semiconductor processing tools may form a via for a semiconductor device. the one or more semiconductor processing tools may deposit a metal plug within the via. the one or more semiconductor processing tools may deposit an oxide-based layer on the metal plug within the via. the one or more semiconductor processing tools may deposit a resistor on the oxide-based layer within the via. the one or more semiconductor processing tools may deposit a first landing pad and a second landing pad on the resistor within the via. the one or more semiconductor processing tools may deposit a first metal plug on the first landing pad and a second metal plug on the second landing pad.
Inventor(s): Chung-Hao Tsai of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chuei-Tang WANG of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Ting Chen of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Hsun Chen of Pingtung County (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Ya Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L21/683, H01L23/00, H01L23/31, H01L23/367, H01L25/00, H01L25/065
Abstract: semiconductor package includes a pair of dies, a redistribution structure, and a conductive plate. dies of the pair of dies are disposed side by side. each die includes a contact pad. redistribution structure is disposed on the pair of dies, and electrically connects the pair of dies. redistribution structure includes an innermost dielectric layer, an outermost dielectric layer, and a redistribution conductive layer. innermost dielectric layer is closer to the pair of dies. redistribution conductive layer extends between the innermost dielectric layer and the outermost dielectric layer. outermost dielectric layer is furthest from the pair of dies. conductive plate is electrically connected to the contact pads of the pair of dies. conductive plate extends over the outermost dielectric layer of the redistribution structure and over the pair of dies. vertical projection of the conductive plate falls on spans of the dies of the pair of dies.
Inventor(s): Sung-Hui Huang of Dongshan Township (TW) for taiwan semiconductor manufacturing co., ltd., Da-Cyuan Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Yu Huang of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Pai Yuan Li of Taichung (TW) for taiwan semiconductor manufacturing co., ltd., Hsiang-Fan Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L23/31, H01L23/367, H01L23/373, H01L23/498, H01L25/00, H01L25/065, H01L25/18
Abstract: a package includes a package component, a device die over and bonded to the package component, a metal cap having a top portion over the device die, and a thermal interface material between and contacting the device die and the metal cap. the thermal interface material includes a first portion directly over an inner portion of the device die, and a second portion extending directly over a corner region of the device die. the first portion has a first thickness. the second portion has a second thickness greater than the first thickness.
Inventor(s): Shih-Wei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tzuan-Horng Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Hung Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/60, H01L21/56, H01L23/00, H01L23/31, H01L25/065
Abstract: a device die including a first semiconductor die, a second semiconductor die, an anti-arcing layer and a first insulating encapsulant is provided. the second semiconductor die is stacked over and electrically connected to the first semiconductor die. the anti-arcing layer is in contact with the second semiconductor die. the first insulating encapsulant is disposed over the first semiconductor die and laterally encapsulates the second semiconductor die. furthermore, methods for fabricating device dies are provided.
Inventor(s): Wen-Shiang LIAO of Toufen Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/66, H01L21/02, H01L23/495, H01L23/522, H01P3/16
Abstract: semiconductor dies in a semiconductor die package may communicate through a dielectric waveguide. the dielectric waveguide may include a high dielectric constant (high-k) core layer that is sandwiched by low dielectric constant (low-k) cladding layers. the difference in dielectric constants of the high-k core layer and the low-k cladding layers enables loose coupling of electromagnetic signal modes in the dielectric waveguide while providing a relatively low critical angle for achieving total internal reflections in the high-k core layer. thus, the combination of semiconductor die package techniques described herein and the dielectric waveguide described herein may enable increased inter-die communication bandwidth while achieving a reduced footprint and increased density for semiconductor die packages.
Inventor(s): Wei-Jhih Mao of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Kuei-Sung Chang of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Shang-Ying Tsai of Pingzhen City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L23/10, H01L23/498, H01L25/00, H01L25/065
Abstract: in some embodiments, the present disclosure relates to an integrated chip including a substrate and a first die disposed over the substrate. a first plurality of die stopper bumps are disposed along a backside of the first die. the first plurality of die stopper bumps directly contact the backside of the first die, and the first plurality of die stopper bumps are arranged as a plurality of groups of die stopper bumps. a plurality of adhesive structures are also present. each of the plurality of adhesive structures surrounds a corresponding group of the plurality of groups of die stopper bumps.
Inventor(s): Guan-Lin CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shi Ning JU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jung-Chien CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Lun CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/088, H01L21/8234
Abstract: a semiconductor device structure, along with methods of forming such, are described. the method includes forming a first dielectric feature between first and the second fin structures, wherein each first and second fin structure includes first semiconductor layers and second semiconductor layers alternatingly stacked and in contact with the first dielectric layer. the method also includes removing the second semiconductor layers so that the first semiconductor layers of the first and second fin structures extend laterally from a first side and a second side of the first dielectric feature, respectively, trimming the first dielectric feature so that the first dielectric feature has a reduced thickness on both first and the second sides, and forming a gate electrode layer to surround each of the first semiconductor layers of the first and second fin structures.
Inventor(s): Jhy-Jyi Sze of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Alexander Kalnitsky of San Francisco CA (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146, H01L21/762
Abstract: various embodiments of the present application are directed towards a semiconductor-on-insulator (soi) dop image sensor and a method for forming the soi dop image sensor. in some embodiments, a semiconductor substrate comprises a floating node and a collector region. a photodetector is in the semiconductor substrate and is defined in part by a collector region. a transfer transistor is over the semiconductor substrate. the collector region and the floating node respectively define source/drain regions of the transfer transistor. a semiconductor mesa is over and spaced from the semiconductor substrate. a readout transistor is on and partially defined by the semiconductor mesa. the semiconductor mesa is between the readout transistor and the semiconductor substrate. a via extends from the floating node to a gate electrode of the readout transistor.
Inventor(s): Sin-Yao Huang of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Chun Wang of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Chi Hung of Chu-Bei City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Tsong Wang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shih Pei Chou of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146
Abstract: some embodiments relate an integrated circuit (ic) including a first substrate. an interconnect structure is disposed over the first substrate. the interconnect structure includes a plurality of metal features that are stacked over one another. a lowermost metal feature of the plurality of metal features is closest to the first substrate, an uppermost metal feature of the plurality of metal features is furthest from the first substrate, and intermediate metal features are disposed between the lowermost metal feature and the uppermost metal feature. a recess extends into the interconnect structure and terminates at a bond pad. a lower surface of the bond pad directly contacts an upper surface of the lowermost metal feature.
Inventor(s): Alan ROTH of Leander TX (US) for taiwan semiconductor manufacturing co., ltd., Eric SOENEN of Austin TX (US) for taiwan semiconductor manufacturing co., ltd., Paul RANNUCI of Leander TX (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01F27/24, H01F17/00, H01F27/28
Abstract: various magnetic thin film inductor structures are disclosed that include one or more magnetic thin film (mtf) materials. during operation, an electric field passes through one or more conductive windings which, in turn, generates a magnetic field for storing energy within these magnetic thin film inductor structures. the magnetic thin film (mtf) materials within these magnetic thin film inductor structures effectively attract magnetic flux lines of this magnetic field. as a result, any magnetic leakage resulting from the magnetic field generated by these magnetic thin film inductor structures onto nearby electrical, mechanical, and/or electro-mechanical devices is lessened when compared to magnetic leakage resulting from the magnetic field generated by other inductor structures not having the one or more mtf materials.
Inventor(s): Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yong-Shiuan Tsair of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/762, H01L21/8238, H01L27/092, H01L29/08, H01L29/10, H01L29/423, H01L29/66
Abstract: an integrated chip comprises a substrate, an isolation structure and a gate structure. the isolation structure is disposed in the substrate and enclosing an active region in the substrate. the active region comprises a source region and a drain region separated by a channel region along a first direction. the gate structure is disposed over the channel region and comprising a first gate electrode region and a second gate electrode region arranged one next to another laterally along a second direction perpendicular to the first direction. the first gate electrode region has a first composition, and the second gate electrode region has a second composition different than the first composition.
Inventor(s): Hsin-Yi Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Lung Hung of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/40, H01L21/28, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/49, H01L29/51, H01L29/66, H01L29/786
Abstract: a device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. the gate electrode includes a first work function metal; a second work function metal over the first work function metal; and a first metal residue at an interface between the first work function metal and the second work function metal, wherein the first metal residue has a metal element that is different than a metal element of the first work function metal.
Inventor(s): Pin Chun SHEN of Changhua (TW) for taiwan semiconductor manufacturing co., ltd., Che Chia CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Li-Ying WU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jen-Hsiang LU of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Chiang HONG of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Wing YEUNG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Sheng LIANG of Changhua (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Hsun CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsien CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L29/06, H01L29/08, H01L29/40, H01L29/423, H01L29/66, H01L29/775
Abstract: the present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. the source/drain contact feature may extend to a lower most of a plurality semiconductor layers.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Chiang HONG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao CHANG of Chu-Bei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
Abstract: semiconductor structures and methods for manufacturing the same are provided. the semiconductor structure includes a gate structure formed over a substrate, and a first source/drain (s/d) structure formed adjacent to the gate structure. the semiconductor structure includes a first contact structure formed over a first side of the first s/d structure, and a portion of the first contact structure is lower than a top surface of the first s/d structure. the semiconductor structure includes a second contact structure formed over a second side of the first s/d structure, and the second contact structure is in direct contact with the first contact structure.
Inventor(s): Huang-Chao CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Sheng LIANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jhon-Jhy LIAW of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L29/06, H01L29/66, H01L29/775, H01L29/786
Abstract: a semiconductor structure includes a substrate, a dielectric wall, and two device units. the dielectric wall has two side surfaces opposite to each other. the two device units are respectively formed at the two side surfaces of the dielectric wall. each of the device units includes channel features, a gate feature and a dielectric filler unit. the channel features are disposed on a corresponding one of the side surfaces of the dielectric wall, and spaced apart from each other. the gate feature is formed around the channel features and disposed on the corresponding one of the side surfaces of the dielectric wall. the dielectric filler unit includes a plurality of first dielectric fillers, each of which is disposed between the dielectric wall and a corresponding one of the channel features. the first dielectric fillers have a dielectric constant greater than that of the dielectric wall.
Inventor(s): Ko-Cheng Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chang-Miao Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L27/088, H01L29/06, H01L29/423, H01L29/51, H01L29/775, H01L29/786
Abstract: the present disclosure provides a method that includes forming a stack including first and second semiconductor layers over a semiconductor substrate, the first and second semiconductor layers having different material compositions and alternating with one another within the stack; forming a dummy gate structure over the stack, the dummy gate structure wrapping around top and sidewall surfaces of the stack; forming a gate spacer on sidewalls of the dummy gate structure and disposed on the top of the stack; forming a dielectric layer with the dummy gate embedded therein; removing the dummy gate structure, resulting in a gate trench; removing the second semiconductor layers through the gate trench such that the first semiconductor layers form semiconductor sheets; forming a metal gate wrapping around the semiconductor sheets; and thereafter, forming a source/drain feature adjacent the metal gate and connecting to the semiconductor sheets.
Inventor(s): Wan-Yi Kao of Baoshan Township (TW) for taiwan semiconductor manufacturing co., ltd., Hung Cheng Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Che-Hao Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Cheng Lu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L29/06, H01L29/423, H01L29/49, H01L29/786
Abstract: semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. in embodiments a dielectric material is deposited for the inner spacer and then treated. the treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.
Inventor(s): Ming-Heng TSAI of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Sheng LIANG of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/775, H01L29/06, H01L29/423, H01L29/66
Abstract: semiconductor structures and methods for manufacturing the same are provided. the semiconductor structure includes a first stack structure extends above the isolation structure, and the first stack structure includes a plurality of first nanostructures along a first direction. the semiconductor structure also includes a second stack structure formed adjacent to the first stack structure, and the second stack structure includes a plurality of second nanostructures along the first direction. a first dielectric wall between the first stack structure and the second stack structure, and the first dielectric wall is directly over a first portion of the isolation structure and surrounded by a second portion of the isolation structure, and a top surface of the first portion of the isolation structure is lower than a top surface of the second portion of the isolation structure.
Inventor(s): Chansyun David YANG of Shinchu (TW) for taiwan semiconductor manufacturing co., ltd., Keh-Jeng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chan-Lon YANG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/8234, H01L29/66
Abstract: the present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.
Inventor(s): Chung-Chiang Wu of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Cheng Chen of Jiaoxi Township (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Chan Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Chin Chung of Pingzhen City (TW) for taiwan semiconductor manufacturing co., ltd., Hsien-Ming Lee of Changhua (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Hao Chen of Chuangwei Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/8234, H01L27/088, H01L29/40, H01L29/423, H01L29/49, H01L29/66
Abstract: a device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. the gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. a low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. the low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. a gate spacer contacts a sidewall of the gate stack.
Inventor(s): Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Han-Jong Chia of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Chen Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Cheng Yang of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ming Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B51/20, H01L23/535, H01L29/417, H10B51/00, H10B51/10, H10B51/30
Abstract: in an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.
Inventor(s): Song-Fu Liao of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Rainer Yen-Chieh Huang of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Hai-Ching Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B51/30, H01L21/768, H10B53/30
Abstract: in some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. a memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. an annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. an amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.
Inventor(s): Tung Ying Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu Chao Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shao-Ming Yu of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N70/00
Abstract: a method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (pcm) layer within the opening and on the bottom electrode, wherein a top surface of the pcm layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the pcm layer.
Inventor(s): Jheng-Hong Jiang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Liang Cheng of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N70/00, H10B63/00
Abstract: a resistive random access memory (rram) device is provided. the rram includes: a bottom electrode via disposed in a first dielectric layer; a bottom electrode electrically connected to the bottom electrode via and protruding upwardly from the bottom electrode via in a vertical direction, wherein the bottom electrode has a tapered shape and includes a base portion extending upwardly from a bottom surface to an interface and a tip portion extending upwardly from the interface to a top surface; a top electrode disposed in a second dielectric layer, the top electrode distanced above and vertically aligned with the bottom electrode; and a switching layer disposed between the first dielectric layer and the second dielectric layer, the switching layer enclosing the bottom electrode, wherein a conductive path between the bottom electrode and the top electrode is formed when a forming voltage is applied.
Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on May 16th, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- B31B50/00
- B31B50/02
- B31B50/07
- B31B50/52
- Taiwan semiconductor manufacturing co., ltd.
- G01K7/01
- H01L23/522
- H01L27/092
- H01L29/78
- G02F1/225
- G02F1/017
- G02F1/025
- G03F7/00
- G03F7/20
- H01L21/027
- H05G2/00
- G06F30/33
- G06F30/3947
- G06F30/39
- G06F30/398
- G03F1/36
- G03F1/70
- G06F30/20
- G11C5/14
- G11C7/12
- G11C7/22
- G11C8/08
- G11C7/10
- G11C11/22
- H10B51/20
- H10B51/30
- G11C11/412
- H01L23/48
- H01L23/528
- H10B10/00
- G11C11/419
- H01J37/147
- H01J37/317
- H01L21/56
- H01L21/67
- H01L21/033
- H01L21/04
- B07C5/34
- G01R31/01
- H01L21/677
- B23Q15/00
- B23Q16/00
- G05D5/04
- H01L23/04
- H01L21/768
- H01L29/66
- H01L23/532
- H01L21/8234
- H01L27/088
- H01L29/06
- H01L27/02
- H01L23/367
- H01L23/00
- H01L23/31
- H01L23/373
- H10B80/00
- H01L21/311
- H01L21/66
- G03F1/42
- G06F30/392
- G06F30/394
- H01L21/321
- H01L23/538
- H01L21/48
- H01L21/683
- H01L25/00
- H01L25/065
- H01L23/498
- H01L25/18
- H01L23/60
- H01L23/66
- H01L21/02
- H01L23/495
- H01P3/16
- H01L23/10
- H01L27/146
- H01L21/762
- H01F27/24
- H01F17/00
- H01F27/28
- H01L21/8238
- H01L29/08
- H01L29/10
- H01L29/423
- H01L29/40
- H01L21/28
- H01L29/49
- H01L29/51
- H01L29/786
- H01L29/417
- H01L29/775
- H01L23/535
- H10B51/00
- H10B51/10
- H10B53/30
- H10N70/00
- H10B63/00
