Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on June 6th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd. on June 6th, 2024
Taiwan Semiconductor Manufacturing Co., Ltd.: 52 patent applications
Taiwan Semiconductor Manufacturing Co., Ltd. has applied for patents in the areas of H01L29/66 (19), H01L27/092 (14), H01L21/8238 (11), H01L29/423 (11), H01L29/78 (10)
With keywords such as: layer, semiconductor, gate, structure, device, region, substrate, portion, source, and dielectric in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s): Ting-Cheng HUANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Tai-Hua YU of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Shui-Ting YANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Chao-Te LEE of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Ching Rong LU of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): A01G25/16, E02B13/02
Abstract: apparatus, systems and methods for irrigating lands are disclosed. in one example, an irrigation system is disclosed. the irrigation system includes a gate and a microcontroller unit (mcu). the gate is configured for adjusting a water flow for irrigating a piece of land. the mcu is configured for controlling the gate to adjust the water flow based on environmental information related to the piece of land.
Inventor(s): Jhih-Fong Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Liqing Wen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Le Lu of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Deng-Gao Chen of Taoyuan (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): A46D3/00, A46B13/00, C08F216/06
Abstract: brushes for cleaning wafers after a chemical mechanical polishing (cmp) process and methods for fabricating such brushes are provided. an exemplary method for fabricating a brush for cleaning wafers after a chemical mechanical polishing (cmp) process includes forming a brush configured for contacting the wafers; and, while forming the brush, controlling formation of pores within the brush to a maximum pore dimension, wherein the maximum pore dimension is 1000 nanometers (nm).
20240181598.MONOLITHIC PLATEN_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Tsung-Lung LAI of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Ping CHEN of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Chung CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Tai PENG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): B24B37/30, B24B37/04, H01L21/306, H01L21/67, H01L21/677
Abstract: in an embodiment, a chemical mechanical planarization (cmp) system includes: a monolithic platen within a platen housing, wherein the monolithic platen is formed of a single piece of material, wherein the monolithic platen includes: a first portion within a first opening, and a second portion within a second opening, wherein the first portion has a different diameter than the second portion; and a polishing fluid delivery module above the monolithic platen, wherein the polishing fluid delivery module is configured to deliver slurry to the monolithic platen during performance of cmp.
Inventor(s): Ting-Jung Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): B81B3/00, B81C1/00, G02B7/02, H04N23/54, H04N23/68
Abstract: the present disclosure relates to an integrated chip structure. the integrated chip structure includes a mems (microelectromechanical systems) actuator. the mems actuator has an anchor. a proof mass continuously wraps around the anchor in a closed loop. one or more curved cantilevers are coupled between the proof mass and a frame. the frame wraps around the proof mass. the one or more curved cantilevers include curved outer surfaces arranged directly between a sidewall of the frame and a sidewall of the proof mass, as viewed in a top-view.
Inventor(s): Po-Wei WANG of Taichung (TW) for taiwan semiconductor manufacturing co., ltd., Chao-Hsing LAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): C23C14/35, C23C14/00, C23C14/34, C23C14/50, H01J37/32, H01J37/34
Abstract: embodiments of the present disclosure provide a substrate processing system. in one embodiment, the system includes a chamber, a target disposed within the chamber, a magnetron disposed proximate the target, a pedestal disposed within the chamber, and a first gas injector disposed at a sidewall of the chamber. the first gas injector includes a first gas channel extending through a body of the first gas injector, the first gas channel has a first gas outlet. the first gas injector also includes a second gas channel extending through the body of the first gas injector, wherein the second gas channel has a second gas outlet. the second gas channel includes a first portion, and a second portion branching off from an end of the first portion, wherein the second portion is disposed at an angle with respect to the first portion, and the first gas injector is operable to rotate about a longitudinal center axis of the body of the first gas injector.
Inventor(s): Chun-Chieh TIEN of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Hsuen CHIANG of Miaoli City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Ming CHEN of Dasi Township (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Ming LIN of Siluo Township (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Wei HUANG of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Hao-Ming CHANG of Pingtung City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Chin LIN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Shien LEE of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F1/32, G03F1/38, G03F1/80, H01L21/308
Abstract: in a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. a resist pattern is formed by using a lithographic operation. the light blocking layer is patterned by using the resist pattern as an etching mask. the phase shift layer is patterned by using the patterned light blocking layer as an etching mask. a border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. the patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. a photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.
Inventor(s): Jiun-Yun LI of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Yuan CHEN of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yao-Chun CHANG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ian HUANG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chiung-Yu CHEN of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G06N10/00, B82Y10/00, H10N60/01, H10N60/80
Abstract: an electronic device includes a pair of depletion gates, an accumulation gate, and a conductive resonator. the depletion gates are spaced apart from each other. the accumulation gate is over the depletion gates. the conductive resonator is over the depletion gates and the accumulation gate. the conductive resonator includes a first portion, a second portion, and a third portion. the first portion and the second portion are on opposite sides of the accumulation gate. the third portion interconnects the first and second portions of the conductive resonator and across the depletion gates. a bottom surface of the first portion of the conductive resonator is lower than a bottom surface of the accumulation gate.
Inventor(s): Philex Ming-Yan FAN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-En HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yih WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jonathan Tsung-Yung CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C7/04, G06F1/20, G11C7/22
Abstract: a system includes a high bandwidth memory (hbm) arranged into portions including memory cells, the hbm further including a differentiated dynamic voltage and frequency scaling (ddvfs) device to perform the following: for a first set of one or more of the memory cells in a first one of the portions, the first set including a first one of the memory cells, controlling a temperature of the first set based on one or more first environmental signals corresponding to at least a first transistor in the first memory cell; and for a second set of one or more of the memory cells in a second one of the portions, the second set including a second one of memory cells, controlling a temperature of the second set based on one or more second environmental signals corresponding to at least a second transistor in the second memory cell.
Inventor(s): Yi-Tzu Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Wei Wu of Caotun Town (TW) for taiwan semiconductor manufacturing co., ltd., Hau-Tai Shieh of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jen Liao of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C11/408, G11C5/02, G11C5/06, G11C11/4093
Abstract: disclosed herein are related to a memory system including unit storage circuits. in one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. in one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. in one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.
Inventor(s): Hung-Li Chiang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Jer-Fu Wang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Iuliana Radu of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C11/412, H01L23/48, H01L29/417, H01L29/423, H01L29/66, H01L29/786, H10B10/00
Abstract: a memory device and a semiconductor die are provided. the memory device includes: a non-volatile storage device, with a first terminal coupled to a bit line; and an access transistor, configured to control electrical connection between a second terminal of the non-volatile storage device and a source line, and comprising an n-type field effect transistor (nfet) and a p-type field effect transistor (pfet) stacked on the nfet. a common source/drain terminal of the nfet and the pfet is coupled to the second terminal of the non-volatile storage device. another common source/drain terminal of the nfet and the pfet is coupled to the source line. further, gate terminals of the nfet and the pfet are coupled to different word lines.
Inventor(s): Chun-Yi Chang of Bade City (TW) for taiwan semiconductor manufacturing co., ltd., Chunyao Wang of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/027, H01L21/308, H01L21/477, H01L29/66
Abstract: as deposited, hard mask thin films have internal stress components which are an artifact of the material, thickness, deposition process of the mask layer as well as of the underlying materials and topography. this internal stress can cause distortion and twisting of the mask layer when it is patterned, especially when sub-micron critical dimensions are being patterned. a stress-compensating process is employed to reduce the impact of this internal stress. heat treatment can be employed to relax the stress, as an example. in another example, a second mask layer with an opposite internal stress component is employed to offset the internal stress component in the hard mask layer.
Inventor(s): Yen-Hao CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Han LAI of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Yu CHANG of Yuansun Village (TW) for taiwan semiconductor manufacturing co., ltd., Chin-Hsiang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/321, H01L21/02, H01L21/027, H01L21/3105
Abstract: a method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. in an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. the third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. the first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.
Inventor(s): Cheng-Kang HU of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Shou-Wen KUO of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Hsiang CHUANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Jiun-Rong PAI of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Hsu-Shui LIU of Pingjhen City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/67, G01M3/38, H01L21/677
Abstract: an apparatus for inspecting wafer carriers is disclosed. in one example, the apparatus includes: a housing; a load port; a robot arm inside the housing; and a processor. the load port is configured to load a wafer carrier into the housing. the robot arm is configured to move a first camera connected to the robot arm. the first camera is configured to capture a plurality of images of the wafer carrier. the processor is configured to process the plurality of images to inspect the wafer carrier.
Inventor(s): Li-Zhen Yu of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Huan-Chieh Su of Tianzhong Township (TW) for taiwan semiconductor manufacturing co., ltd., Lin-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L21/02, H01L23/528, H01L23/532, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/78, H01L29/786
Abstract: semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. in an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.
Inventor(s): Che-Lun Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Pin Lin of Xinpu Township (TW) for taiwan semiconductor manufacturing co., ltd., Yuan-Ching Peng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L21/306, H01L21/762, H01L23/522, H01L23/532, H01L29/06, H01L29/08, H01L29/417, H01L29/423, H01L29/45, H01L29/66, H01L29/786
Abstract: an integrated circuit (ic) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. the source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. the front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. the backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. the backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.
Inventor(s): Kuo-Cheng CHING of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao Wang of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Lun Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L23/535, H01L27/088, H01L29/06, H01L29/08, H01L29/10, H01L29/161, H01L29/165, H01L29/66
Abstract: the present disclosure describes a method to reduce power consumption in a fin structure. for example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. the method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.
Inventor(s): Te-An CHEN of Beitun District (TW) for taiwan semiconductor manufacturing co., ltd., Meng-Han LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L21/8238, H01L27/092, H01L29/08, H01L29/423, H01L29/66, H01L29/78
Abstract: in a method of manufacturing a semiconductor device, an isolation structure is formed in a substrate defining an active region, a first gate structure is formed over the isolation structure and a second gate structure over the active region adjacent to the first gate structure, a cover layer is formed to cover the first gate structure and a part of the active region between the first gate structure and the second gate structure, the active region between the first gate structure and the second gate structure not covered by the cover layer is etched to form a recess, and an epitaxial semiconductor layer is formed in the recess.
Inventor(s): Shih-Yao Lin of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Te-Yung Liu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L27/088, H01L27/092
Abstract: a method includes forming a first protruding semiconductor fin and a dummy fin protruding higher than top surfaces of isolation regions. the first protruding semiconductor fin is parallel to the dummy fin, forming a gate stack on a first portion of the first protruding semiconductor fin and a second portion of the dummy fin. the method further includes recessing a third portion of the first protruding semiconductor fin to form a recess, recessing an fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin, and forming an epitaxy semiconductor region in the recess. the epitaxy semiconductor region is grown toward the dummy fin.
Inventor(s): Feng-Ching Chu of Pingtung County (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Pin Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L21/02, H01L21/8238, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/786
Abstract: a method of manufacturing an integrated circuit (ic) includes providing a structure having a fin over a substrate in a region of the ic, a sacrificial gate stack engaging a channel region of the fin, and gate spacers on sidewalls of the sacrificial gate stack. the first layers and the second layers are alternately stacked over the substrate. the method also includes etching the fin adjacent the gate spacers, resulting in source/drain trenches, partially recessing the second layers exposed in the source/drain trenches, resulting in gaps between adjacent layers of the first layers in the fin, depositing inner spacer features in the gaps in the fin, epitaxially growing source/drain features in the source/drain trenches, and replacing the sacrificial gate stack with a metal gate stack. the metal gate stack includes a gate dielectric layer disposed over top and sidewalls of the fin having both the first and the second layers.
Inventor(s): Yung-Hsiang CHAN of Taichung (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Hung HUANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Shan-Mei LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jian-Hao CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Feng YU of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Kuei-Lun LIN of Keelung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8234, H01L21/8238, H01L27/088, H01L29/423, H01L29/66, H01L29/786
Abstract: a semiconductor device includes a first semiconductor layer below a second semiconductor layer; first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and a gate electrode surrounding both the first and the second gate dielectric layers. the first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer. the second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer. the first top section has a first thickness. the second top section has a second thickness. the second thickness is greater than the first thickness.
Inventor(s): Chung-Liang Cheng of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Ziwei Fang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8238, H01L21/02, H01L21/28, H01L27/092, H01L29/423, H01L29/66, H01L29/78, H01L29/786
Abstract: a method of manufacturing a semiconductor device is provided. a substrate is provided. the substrate has a first region and a second region. an n-type work function layer is formed over the substrate in the first region but not in the second region. a p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. the p-type work function layer directly contacts the substrate in the second region. and the p-type work function layer includes a metal oxide.
Inventor(s): Cheng-I Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Wei Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ting-Hsiang Chang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Tang Peng of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Cheng Lu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8238, H01L21/762, H01L27/092
Abstract: in an embodiment, a method includes: forming a first fin and a second fin over a semiconductor substrate; forming an isolation region between the first fin and the second fin, forming the isolation region comprising: depositing an oxide liner along the first fin, the second fin, and the semiconductor substrate, the oxide liner comprising a first upper portion and a first lower portion along the first fin, the first lower portion being between the first upper portion and the semiconductor substrate; thinning the oxide liner; depositing an insulation material over the oxide liner; and recessing the insulation material; and forming a gate structure over the first fin, the second fin, and the isolation region.
Inventor(s): Chih-Tsung Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chewn-Pu Jou of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Stefan Rusu of Sunnyvale CA (US) for taiwan semiconductor manufacturing co., ltd., Feng-Wei KUO of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/34
Abstract: a semiconductor structure includes a semiconductor substrate, a semiconductor device and a heating structure. the semiconductor substrate includes a device region and a heating region surrounding the device region. the semiconductor device is located on the device region. the heating structure is located on the heating region and includes an intrinsic semiconductor area, at least one heating element and at least one heating pad. the intrinsic semiconductor area is surrounding the semiconductor device. the at least one heating element is located at a periphery of the intrinsic semiconductor area. the at least one heating pad is joined with the at least one heating element, wherein the at least one heating pad includes a plurality of contact structures, and a voltage is supplied from the plurality of contact structures to control a temperature of the at least one heating element.
Inventor(s): Shu-Cheng Chin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kong-Beng Thei of Pao-Shan Village (TW) for taiwan semiconductor manufacturing co., ltd., Jung-Hui Kao of Hsin-Chen (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Ting Hsiao of Miaoli County (TW) for taiwan semiconductor manufacturing co., ltd., Kuei-Kai Hou of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L23/00, H01L23/498
Abstract: an integrated chip including a substrate and a transistor device along the substrate. a plurality of conductive interconnects are over the transistor device. a first under-bump metal (ubm) layer is over the conductive interconnects. a first metal bump is directly over the first ubm layer. a metal-insulator-metal (mim) capacitor array is over the transistor device and under the first ubm layer. the mim capacitor array includes a first mim capacitor and a second mim capacitor coupled in parallel and disposed directly under the first ubm layer.
Inventor(s): Hsing-Lien Lin of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Chin-Wei Liang of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Hsun-Chung Kuang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ching Ju Yang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528
Abstract: an interfacial layer is provided that binds a hydrophilic interlayer dielectric to a hydrophobic gap-filling dielectric. the hydrophobic gap-filling dielectric extends over and fill gaps between devices in an array of devices disposed between two metal interconnect layers over a semiconductor substrate and is the product of a flowable cvd process. the interfacial layer provides a hydrophilic upper surface to which the interlayer dielectric adheres. optionally, the interfacial layer is also the product of a flowable cvd process. alternatively, the interfacial layer may be silicon nitride or another dielectric that is hydrophilic. the interfacial layer may have a wafer contact angle (wca) intermediate between a wca of the hydrophobic dielectric and a wca of the interlayer dielectric.
Inventor(s): Te-Hsin CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Wei PENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Cheng LIN of Taichung (TW) for taiwan semiconductor manufacturing co., ltd., Jiann-Tyng TZENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jiun-Wei LU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/528, H01L21/38, H01L21/768
Abstract: an integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. the multiple backside conductive layers each includes conductive segments. the conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. the conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.
Inventor(s): Yu-Hung Lin of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., An-Jhih Su of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Der-Chyang Yeh of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Guo Shen of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Nan Yuan of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Shih Yeh of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L23/31, H01L25/00, H01L25/065
Abstract: a method of manufacturing a semiconductor device includes the following steps. a semiconductor substrate is provided. a plurality of dielectric layers and a plurality of first conductive features in the dielectric layers are formed on the semiconductor substrate. at least one polymer layer and a plurality of second conductive features in the at least one polymer layer on the dielectric layers are formed. a plurality of conductive connectors are formed to electrically connect to the second conductive features. the semiconductor substrate, the dielectric layers and the at least one polymer layer are cut into a plurality of dies.
20240186257.SEMICONDUCTOR DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Meng-Che TU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Po-Nan YEH of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Miao-Ken HUNG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Po-Han WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Hsiang HU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jui KUO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/538, H01L23/00, H01L23/48, H01L23/522
Abstract: according to one embodiment, a semiconductor device is provided. the semiconductor device includes a first semiconductor module, a redistribution layer (rdl) module and a second semiconductor module. the rdl module is disposed on the first semiconductor module. the rdl module includes a plurality of polymer layers and a plurality of vias. the polymer layers are stacked on the first semiconductor module. the vias are disposed within the polymer layers. the second semiconductor module is disposed on the rdl module. a height difference of a top surface of at least one of the polymer layers ranges from 0 um to 1 um; or an angle between a sidewall and a bottom surface of at least one of the vias ranges from 90� to 95�; or a glass transition temperature (tg) of at least one of the polymer layers is larger than 260� c.
Inventor(s): Yeong-Jyh Lin of Caotun Township (TW) for taiwan semiconductor manufacturing co., ltd., Ching I Li of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., De-Yang Chiou of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Sz-Fan Chen of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Han-Jui Hu of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Hung Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ru-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Yi Yu of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/544, G03F1/42, G03F1/70, H01L21/027, H01L21/66, H01L21/683
Abstract: various embodiments of the present disclosure are directed towards a method for forming an integrated chip. an alignment process is performed on a first semiconductor workpiece and a second semiconductor workpiece by virtue of a plurality of workpiece pins. the first semiconductor workpiece is bonded to the second semiconductor workpiece. a shift value is determined between the first and second semiconductor workpieces by virtue of a first plurality of alignment marks on the first semiconductor workpiece and a second plurality of alignment marks on the second semiconductor workpiece. a layer of an integrated circuit (ic) structure is formed over the second semiconductor workpiece based at least in part on the shift value.
Inventor(s): Chao-Wei Chiu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jen-Jui Yu of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hsuan-Ting Kuo of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Shiuan Wong of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsiu-Jen Lin of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L23/498, H01L25/065
Abstract: semiconductor devices including the use of solder materials and methods of manufacturing are provided. in embodiments the solder materials utilize a first tensile raising material, a second tensile raising material, and a eutectic modifier material. by utilizing the materials a solder material can be formed and used with a reduced presence of needles that may otherwise form during the placement and use of the solder material.
Inventor(s): Shenggao Li of Cupertino CA (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L23/48, H01L23/498, H01L23/538, H01L25/00, H01L25/065
Abstract: a method includes forming a first package component, and forming a first plurality of electrical connectors at a first surface of the first package component. the first plurality of electrical connectors are laid out as having a honeycomb pattern. a second package component is bonded to the first package component, wherein a second plurality of electrical connectors at a second surface of the second package component are bonded to the first plurality of electrical connectors.
Inventor(s): Jhih-Yu Wang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Hsiang Hu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Sih-Hao Liao of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Chi Chu of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L23/544, H01L25/065
Abstract: an integrated fan-out (info) package includes a die, an encapsulant laterally encapsulating the die, and a redistribution structure. the redistribution structure is disposed on the encapsulant. the redistribution structure includes a plurality of routing patterns and a plurality of alignment marks. the routing patterns are electrically connected to the die. the alignment marks surround the routing patterns. the alignment marks are electrically insulated from the die and the routing patterns. at least one of the alignment marks is in physical contact with the encapsulant, and the alignment marks located at different level heights are arranged in a non-overlapping manner vertically.
Inventor(s): Kai-Fung CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chin-Wei LIANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Feng WENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Yu YEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., CHEYU LIU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Chih CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Yang LEI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., CHING-HUA HSIEH of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Chou LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/18, H01L21/56, H01L23/00, H01L23/31, H01L23/498, H01L23/538, H01L25/00
Abstract: a semiconductor device and a manufacturing method thereof are provided. the semiconductor device includes a redistribution layer (rdl) module, a first semiconductor module, an interconnection module, a second semiconductor module and a molding material. the first semiconductor module is disposed on the rdl module. the interconnection module is disposed on the rdl module. the second semiconductor module is disposed on the interconnection module. the molding material covers the rdl module and surrounds the first semiconductor module and the second semiconductor module. a top surface of the first semiconductor module and a top surface of the second semiconductor module are exposed by the molding material.
Inventor(s): Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/02, H01L27/092, H10B10/00
Abstract: the static random access memory (sram) cell of the present disclosure includes a first pull-down device, a second pull-down device, a first pass-gate device, and a second pass-gate device in a first p-well on a substrate; a third pull-down device, a fourth pull-down device, a third pass-gate device, and a fourth pass-gate device in a second p-well on the substrate; a first pull-up device and a second pull-up device in an n-well between the first p-well and the second p-well; and a first landing pad between the second pull-down device and the first pull-up device. the first landing pad is electrically coupled to a gate structure of the second pass-gate device by way of a first gate via.
Inventor(s): Jhon Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/02, G11C11/412, H01L23/522, H01L23/528, H10B10/00
Abstract: a semiconductor device including a static random access memory (sram) device includes a first sram array including a first plurality of bit cells arranged in a matrix; a second sram array including a second plurality of bit cells arranged in a matrix; and a plurality of abutting dummy cells disposed between the first sram array and the second sram array. each of the plurality of abutting dummy cells includes a plurality of dummy gate electrode layers and a plurality of dummy contacts. the semiconductor device further includes a first-type well continuously extending from the first sram array to the second sram array. the first-type well is in direct contact with portions of the plurality of dummy contacts.
Inventor(s): Yi-Huan Chen of Hsin Chu City (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Chih Chou of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ta-Wei Lin of Minxiong Township (TW) for taiwan semiconductor manufacturing co., ltd., Hsiao-Chin Tuan of Taowan (TW) for taiwan semiconductor manufacturing co., ltd., Alexander Kalnitsky of San Francisco CA (US) for taiwan semiconductor manufacturing co., ltd., Kong-Beng Thei of Pao-Shan Village (TW) for taiwan semiconductor manufacturing co., ltd., Shi-Chuang Hsiao of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Hong Kuo of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/088, H01L29/423, H01L29/66, H01L29/78
Abstract: in some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. a conductive gate is disposed over a doped region of the substrate. a gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. a bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. first and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. an inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. a drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.
Inventor(s): Meng-Yu LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Fu CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hsiang-Hung HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L23/528
Abstract: an integrated circuit includes a plurality of transistors and a vertical local interconnection. the transistors include a plurality of gate components, a plurality of front-side source/drain epitaxies and a plurality of back-side source/drain epitaxies, wherein the front-side source/drain epitaxies are closer to a front-side side of the integrated circuit than the back-side source/drain epitaxies. the vertical local interconnection connects a first connected-one of the front-side source/drain epitaxies with a second connected-one of the back-side source/drain epitaxies. a covered-one of the gate components is located between the first connected-one and the second connected-one, the covered-one comprises an front-side portion, a back-side portion and a covered portion connecting the front-side portion with the back-side portion, and the vertical local interconnection crosses the covered portion and exposes the front-side portion and the back-side portion.
Inventor(s): Ta-Pen GUO of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Lee-Chung LU of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Li-Chun TIEN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/118, H01L27/02, H01L27/092, H01L29/66, H01L29/78
Abstract: a semiconductor device includes a plurality of standard cells. the plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. the first group of standard cells and the second group of standard cells are arranged in a column direction. a cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.
20240186356.IMAGE SENSOR_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Min-Feng Kao of Chiayi City (TW) for taiwan semiconductor manufacturing co., ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Chang Kuo of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Chau Chen of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Chi Hung of Hsin-Chu County (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Chan Li of Tainan CIty (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146, H01L21/762
Abstract: image sensors and methods for forming the same are provided. a semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, a metal grid disposed directly over the plurality of metal isolation features, and a plurality of microlens features disposed over the metal grid.
Inventor(s): Kai-Hsuan Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Bo-Yu Lai of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Sai-Hooi Yeong of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Cheng Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Yih-Ann Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Ming Chen of Hsin-Chu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/764, H01L21/768, H01L21/8238, H01L23/10, H01L29/66
Abstract: in one example aspect, a method for integrated circuit (ic) fabrication comprises providing a device structure including a substrate, a source/drain (s/d) feature on the substrate, a gate stack on the substrate, a contact hole over the s/d feature; and a dummy feature over the s/d feature and between the gate stack and the contact hole. the method further comprises forming in the contact hole a contact plug that is electrically coupled to the s/d feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. the method further comprises forming over the contact plug a seal layer that covers the air gap.
Inventor(s): Po-Yu Lin of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Pin Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Tzu-Hua Chiu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Hao Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Han Fan of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd., Li-Li Su of HsinChu County (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Min Liu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/02, H01L21/306, H01L29/423, H01L29/66, H01L29/786
Abstract: a semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. the semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
Inventor(s): Wei Ju LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Fu CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Wei WU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Zhiqiang WU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L21/285, H01L21/8238, H01L27/092, H01L29/08, H01L29/45
Abstract: semiconductor device includes a substrate having a plurality of fins formed from the substrate, a first source/drain feature comprising a first epitaxial layer in contact with a first fin of the plurality of fins, and a second epitaxial layer formed over the first epitaxial layer, the second epitaxial layer comprising a first facet and a second facet connecting to the first facet, a second source/drain feature disposed adjacent to the first source/drain feature, the second source/drain feature comprising a first epitaxial layer in contact with a second fin of the plurality of fins a second epitaxial layer formed over the first epitaxial layer of the second source/drain feature, the second epitaxial layer of the second source/drain feature comprising a third facet and a fourth facet connecting to the third facet, and a third epitaxial layer comprising a first center portion disposed above and in contact with the first facet and the second facet, and a second center portion disposed above and in contact with the third facet and the fourth facet.
Inventor(s): Yu-Chi PAN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ying-Liang Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Hsi Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Bin Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/28, H01L21/311, H01L21/8234, H01L21/8238, H01L27/088, H01L27/092, H01L29/51, H01L29/66, H01L29/78
Abstract: a semiconductor device includes a fin structure disposed over a substrate. the semiconductor device includes a gate dielectric layer disposed over the fin structure. the semiconductor device includes an interfacial layer over a top portion of the gate dielectric layer. a bottom portion of gate dielectric layer is free of contact with the interfacial layer. the semiconductor device includes a gate structure straddling the fin structure.
Inventor(s): Yu-Chen Chang of Taoyuan (TW) for taiwan semiconductor manufacturing co., ltd., Anhao Cheng of Taichung (TW) for taiwan semiconductor manufacturing co., ltd., Meng-I Kang of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Liang Lin of Tainan (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8238, H01L21/28, H01L27/092, H01L29/49
Abstract: in accordance with some aspects of the disclosure, a semiconductor structure is provided. the semiconductor structure includes: an active region; and a gate stack disposed on the active region. the gate stack includes: at least one gate dielectric layer disposed on the active region; and a metal gate structure disposed on the at least one gate dielectric layer. the metal gate structure includes: a metal gate layer comprising a first material; and at least one dummy structure disposed in the metal gate layer, the at least one dummy structure extending vertically through an entire thickness of the metal gate structure and comprising a second material. the second material is different from the first material.
Inventor(s): Po-Yu Chen of Baoshan Township (TW) for taiwan semiconductor manufacturing co., ltd., Wan-Hua Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jing-Ying Chen of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Ming Wu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L29/06, H01L29/10, H01L29/45, H01L29/49, H01L29/66
Abstract: a device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.
Inventor(s): Cheng-Ming LIN of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Sai-Hooi YEONG of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Ziwei FANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Bo-Feng YOUNG of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Chi On CHUI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Yu CHANG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Huang-Lin CHAO of Hillsboro OR (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L21/28, H01L29/51, H01L29/66
Abstract: the present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. the semiconductor device includes a gate stack between the first and second spacers. the gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. the first portion includes a crystalline material and the second portion comprises an amorphous material. the gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.
Inventor(s): Chih-Yu Ma of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shahaji B. More of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Min Huang of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Chieh Chang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/8238, H01L27/092, H01L29/08, H01L29/66
Abstract: a device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. the epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. the epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.
Inventor(s): Yu-Chao LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Sheng YUN of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Tung-Ying LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L29/06, H01L29/66
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes first nanostructures and second nanostructures formed over a substrate, and a first gate structure formed over the first nanostructures. the semiconductor device structure includes a second gate structure formed over the second nanostructures, and the second gate structure includes a gate dielectric layer, a first type work function layer and a filling layer. the semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, and the first isolation layer includes a first sidewall surface, and the first sidewall surface is in direct contact with a first interface between the gate dielectric layer and the first type work function layer and a second interface between the work function layer and the filling layer.
20240186967.AMPLIFIER CIRCUIT_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Wei Shuo LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03F3/45
Abstract: a first embodiment is directed to a circuit including a positive biasing circuit with a drive pmos for biasing in subthreshold, a negative biasing circuit with a drive nmos for biasing in subthreshold, and an amplification circuit coupled to the biasing circuits. the amplification circuit includes a first stage with a first boosting stage, a second stage with a second boosting stage, and a resistive element coupled between the first and second stages. a second embodiment is directed to a folded cascode operational amplifier wherein a value of the resistive element is selected to place at least one of a drive mos in subthreshold. a third embodiment is directed to an integrated circuit with a resistive area neighboring a first boosting area and a second boosting area, the resistive area including a resistive element directly connected to a drive pmos and a drive nmos.
Inventor(s): Josh Lin of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Ta Hsieh of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Ming Huang of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Wei Ho of Tainan (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B41/30, H01L21/768, H01L23/485, H01L29/423, H01L29/66, H10B41/10, H10B41/40, H10B41/42
Abstract: the present disclosure, in some embodiments, relates to a method of forming an integrated chip. the method includes forming a first conductive structure over a substrate. a first intermediate sidewall spacer is formed to surround the first conductive structure. a masking material is formed over the substrate and around the first intermediate sidewall spacer. a part of the first intermediate sidewall spacer protrudes outward from the masking material. the part of the first intermediate sidewall spacer that protrudes outward from the masking material is etched to form a first sidewall spacer.
Inventor(s): Sheng-Chih Lai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N70/20, G11C13/00, H10N70/00
Abstract: a method includes forming a bottom electrode, forming a dielectric layer, forming a phase-change random access memory (pcram) region in contact with the dielectric layer, and forming a top electrode. the dielectric layer and the pcram region are between the bottom electrode and the top electrode. a filament is formed in the dielectric layer. the filament is in contact with the dielectric layer.
Inventor(s): Chih-Yang Chang of Yuanlin Township (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Ting Chu of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N70/00, H10B63/00, H10N70/20
Abstract: some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. a memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. an upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.
Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on June 6th, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- A01G25/16
- E02B13/02
- Taiwan semiconductor manufacturing co., ltd.
- A46D3/00
- A46B13/00
- C08F216/06
- B24B37/30
- B24B37/04
- H01L21/306
- H01L21/67
- H01L21/677
- B81B3/00
- B81C1/00
- G02B7/02
- H04N23/54
- H04N23/68
- C23C14/35
- C23C14/00
- C23C14/34
- C23C14/50
- H01J37/32
- H01J37/34
- G03F1/32
- G03F1/38
- G03F1/80
- H01L21/308
- G06N10/00
- B82Y10/00
- H10N60/01
- H10N60/80
- G11C7/04
- G06F1/20
- G11C7/22
- G11C11/408
- G11C5/02
- G11C5/06
- G11C11/4093
- G11C11/412
- H01L23/48
- H01L29/417
- H01L29/423
- H01L29/66
- H01L29/786
- H10B10/00
- H01L21/027
- H01L21/477
- H01L21/321
- H01L21/02
- H01L21/3105
- G01M3/38
- H01L21/768
- H01L23/528
- H01L23/532
- H01L29/06
- H01L29/78
- H01L21/762
- H01L23/522
- H01L29/08
- H01L29/45
- H01L21/8234
- H01L23/535
- H01L27/088
- H01L29/10
- H01L29/161
- H01L29/165
- H01L21/8238
- H01L27/092
- H01L21/28
- H01L23/34
- H01L23/00
- H01L23/498
- H01L21/38
- H01L23/538
- H01L21/48
- H01L23/31
- H01L25/00
- H01L25/065
- H01L23/544
- G03F1/42
- G03F1/70
- H01L21/66
- H01L21/683
- H01L25/18
- H01L21/56
- H01L27/02
- H01L27/118
- H01L27/146
- H01L21/764
- H01L23/10
- H01L21/285
- H01L21/311
- H01L29/51
- H01L29/49
- H03F3/45
- H10B41/30
- H01L23/485
- H10B41/10
- H10B41/40
- H10B41/42
- H10N70/20
- G11C13/00
- H10N70/00
- H10B63/00
