Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on July 4th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd. on July 4th, 2024
Taiwan Semiconductor Manufacturing Co., Ltd.: 58 patent applications
Taiwan Semiconductor Manufacturing Co., Ltd. has applied for patents in the areas of H01L29/423 (13), H01L29/66 (12), H01L29/06 (11), H01L21/8234 (9), H01L23/00 (9) H01L29/0673 (4), H01L29/42392 (2), H01L21/0274 (2), B24B37/005 (1), H01L27/0262 (1)
With keywords such as: structure, layer, semiconductor, gate, device, dielectric, substrate, drain, source, and voltage in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s): Che-Liang CHUNG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Che-Hao TU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kei-Wei CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Wen LIU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): B24B37/005, B24B51/00, H01L21/67
CPC Code(s): B24B37/005
Abstract: the present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. multiple zones are identified on a surface of a wafer. the cmp target is achieved on each zone in a sequence of cmp processes. each cmp process in the sequence achieves the cmp target for only one zone, using a cmp process selective to other zones.
Inventor(s): Shang-Yu Wang of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Hao Kung of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Hsiang Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kei-Wei Chen of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Hui-Chi Huang of Zhubei (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): B24B37/10, B24B37/04, B24B49/00, H01L21/306
CPC Code(s): B24B37/107
Abstract: a method includes placing a polisher head on platen, the polisher head including a set of first magnets, and controlling a set of second magnets to rotate the polisher head on the platen, wherein controlling the set of second magnets includes reversing the polarity of at least one second magnet of the set of second magnets to produce a magnetic force on at least one first magnet of the set of first magnets, wherein the set of second magnets are external to the polisher head.
Inventor(s): Weiwei SONG of San Jose CA (US) for taiwan semiconductor manufacturing co., ltd., Stefan RUSU of Sunnyvale CA (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G02B6/12, G02B6/122, G02B6/13, G06N3/067
CPC Code(s): G02B6/12002
Abstract: photonic device, system and methods of making photonic devices and systems, the method including: providing a substrate, forming an insulator layer over the substrate, depositing a plurality of waveguide layers and a plurality of insulator spacers at different vertical levels over the insulator layer, wherein adjacent waveguide layers in the plurality of waveguide layers are isolated by one or more insulator spacers in the plurality of insulator spacers, and forming a plurality of waveguide patterns at the plurality of waveguide layers, wherein at least two waveguide patterns at different vertical levels in the plurality of waveguide patterns are coupled.
Inventor(s): Chih-Tsung Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chewn-Pu Jou of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Felix Yingkit Tsui of Cupertino CA (US) for taiwan semiconductor manufacturing co., ltd., Stefan Rusu of Sunnyvale CA (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G02B6/122, G02B6/125
CPC Code(s): G02B6/1228
Abstract: a structure includes a first waveguide and a second waveguide. the first waveguide includes a first strip portion and a first tapered tip portion connected to the first strip portion. the second waveguide includes a second strip portion and a second tapered tip portion connected to the second strip portion, wherein the first tapered tip portion of the first waveguide is optically coupled to the second tapered tip portion of the second waveguide, and the first waveguide and the second waveguide are configured to guide a light. in a region where the light is coupled between the first tapered tip portion and the second tapered tip portion, an effective refractive index of the first waveguide with respect to the light is substantially equal to an effective refractive index of the second waveguide with respect to the light.
Inventor(s): Haohua Zhou of Freemont CA (US) for taiwan semiconductor manufacturing co., ltd., Mei Hsu Wong of Saratoga CA (US) for taiwan semiconductor manufacturing co., ltd., Tze-Chiang Huang of Saratoga CA (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G05F1/46, H03K5/003
CPC Code(s): G05F1/46
Abstract: a semiconductor device includes an analog voltage regulator and an integrated circuit module. the analog voltage regulator generates a regulated output voltage. the integrated circuit module generates an analog sense voltage based on the regulated output voltage and includes integrated circuit dies, a first sensor, second sensors, and a digital voltage offset controller (dvoc). the first sensor generates a digital reference voltage based on an analog reference voltage. the second voltage sensors detect voltages at predetermined locations on the integrated circuit dies. the dvoc generates a digital offset voltage substantially equal to the difference between the digital reference voltage and the voltage detected by a selected one of the second voltage sensors. the regulated output voltage is based on an unregulated input voltage, the analog sense voltage, and the digital offset voltage.
Inventor(s): Sanjeev Kumar JAIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ishan KHERA of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Atul KATOCH of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C11/408, G11C11/4076, G11C11/4093, H03K19/20
CPC Code(s): G11C11/4087
Abstract: a memory circuit includes a global control circuit, a first local control circuit and a first set of word line post-decoder circuits. the global control circuit is configured to generate a first and second set of global pre-decoder signals and a first set of local address signals. the first local control circuit includes a first set of repeater circuits and a first clock pre-decoder circuit. the first set of repeater circuits is configured to generate a first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and a second set of local pre-decoder signals in response to the second set of global pre-decoder signals. the first clock pre-decoder circuit is configured to generate a first and second set of clock signals. the first set of word line post-decoder circuits is configured to generate a first set of word line signals.
Inventor(s): Hiroki Noguchi of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ku-Feng Lin of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yih Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C29/42, G11C29/20, G11C29/24, G11C29/44
CPC Code(s): G11C29/42
Abstract: a memory device includes: a memory cell array comprising a plurality of memory cells, the plurality of memory cells comprising a plurality of data memory cells including a first data memory cell and a plurality of backup memory cells including a first backup memory cell; a storage storing an error table configured to record errors in the plurality of data memory cells, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data memory cell and having an address and a failure count; and a controller configured to replace the first data memory cell with the first backup memory cell based on the error table.
Inventor(s): Hsiao-Tsung YEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Wei LUO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01F21/12
CPC Code(s): H01F21/12
Abstract: a semiconductor device includes a first conductive winding over a first substrate. the semiconductor device further includes a second substrate bonded to the first substrate. the semiconductor device further includes a switch in the second substrate. the semiconductor device further includes an inter-level via (ilv) in the second substrate. the semiconductor device further includes a second conductive winding over the second substrate, wherein the second conductive winding includes a conductive line around a central opening, the switch is electrically connected to the second conductive winding on a first side of the opening, and the ilv is electrically connected to the second conductive winding on a second side of the opening opposite the first side.
Inventor(s): Chansyun David YANG of Shinchu (TW) for taiwan semiconductor manufacturing co., ltd., Keh-Jeng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chan-Lon YANG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Perng-Fei YUH of Walnut Creek CA (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01J37/305, H01J37/08
CPC Code(s): H01J37/3053
Abstract: the present disclosure relates to an ion beam etching (ibe) system including a plasma chamber configured to provide plasma, a screen grid, an extraction grid, an accelerator grid, and a decelerator grid. the screen grid receives a screen grid voltage to extract ions from the plasma within the plasma chamber to form an ion beam through a hole. the extraction grid receives an extraction grid voltage, where a voltage difference between the screen grid voltage and the extraction grid voltage determines an ion current density of the ion beam. the accelerator grid receives an accelerator grid voltage. a voltage difference between the extraction grid voltage and the accelerator grid voltage determines an ion beam energy for the ion beam. the ibe system can further includes a deflector system having a first deflector plate and a second deflector plate around a hole to control the direction of the ion beam.
Inventor(s): Yu-Hsiang CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Bo-Lin WU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01J37/32, C23C16/458, H01L21/66, H01L21/677
CPC Code(s): H01J37/3288
Abstract: the present disclosure relates to methods of processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. the chemical vapor deposition chamber includes a spindle mechanism that cooperates with one or more carrier ring forks to move the semiconductor substrate from one station to another station. the methods include monitoring one or more spindle operation parameters and carrying out one or more maintenance steps on the spindle mechanism based on the results of monitoring the one or more spindle operation parameters. the monitored spindle operation parameters provide an indication of undesirable vibration of the semiconductor substrates in the processing chamber. the vibration of the semiconductor substrates in the processing chamber is undesirable because it promotes generation of unwanted particles that deposit onto a surface of the semiconductor substrate.
Inventor(s): Chia-Ching Lee of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Chiang Wu of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Hang Chiu of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Hsuan-Yu Tung of Keelung (TW) for taiwan semiconductor manufacturing co., ltd., Da-Yuan Lee of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/02, H01L21/768, H01L27/088, H01L29/66
CPC Code(s): H01L21/02175
Abstract: a method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. the first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. the method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.
Inventor(s): Xianhui ZHOU of Shanghai City (CN) for taiwan semiconductor manufacturing co., ltd., Lei WANG of Shanghai City (CN) for taiwan semiconductor manufacturing co., ltd., Jie CHEN of Shanghai City (CN) for taiwan semiconductor manufacturing co., ltd., Zihao ZHANG of Shanghai City (CN) for taiwan semiconductor manufacturing co., ltd., Renqin LIAO of Shanghai City (CN) for taiwan semiconductor manufacturing co., ltd., Jilong GU of Shanghai City (CN) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/027, H01L21/033, H01L21/677
CPC Code(s): H01L21/0274
Abstract: a method includes performing a coating process on a first one of wafers to form a photoresist layer using a coating tool; after performing the coating process, retrieving the first one of the wafers to a cassette docked on the coating tool; transferring the cassette from the coating tool to a load port of an exposure tool external to the coating tool; transferring the first one of the wafers from the cassette on the load port of the exposure tool to a wafer stage of the exposure tool; performing an exposing process on the first one of the wafers to pattern the photoresist layer on the first one of the wafers.
Inventor(s): Tung-Hung FENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hui-Chun LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Wen JIANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Che WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/027, G03F7/00, G03F7/16, H01L21/033, H01L21/67, H01L21/687
CPC Code(s): H01L21/0274
Abstract: in a method of coating a photo resist over a wafer, dispensing the photo resist from a nozzle over the wafer is started while rotating the wafer, and dispensing the photo resist is stopped while rotating the wafer. after starting and before stopping the dispensing the photo resist, a wafer rotation speed is changed at least 4 times. during dispensing, an arm holding the nozzle may move horizontally. a tip end of the nozzle may be located at a height of 2.5 mm to 3.5 mm from the wafer.
Inventor(s): Yi-Chen LO of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Shan CHEN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Kai YANG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Pinyen LIN of Rochester NY (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/311, H01L21/033, H01L21/66
CPC Code(s): H01L21/31144
Abstract: in a method of forming a pattern over a semiconductor substrate, a target layer to be patterned is formed over a substrate, a mask pattern including an opening is formed in a mask layer, a shifting film is formed in an inner sidewall of the opening, a one-directional etching operation is performed to remove a part of the shifting film and a part of the mask layer to form a shifted opening, and the target layer is patterned by using the mask layer with the shifted opening as an etching mask. a location of the shifted opening is laterally shifted from an original location of the opening.
Inventor(s): Chih-Chuan Yang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chang-Ta Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/762, H01L21/3065, H10B10/00
CPC Code(s): H01L21/76224
Abstract: a method includes receiving a structure that includes a substrate including a first well region having a first dopant type and a second well region having a second dopant type that is opposite to the first dopant type; and fins extending above the substrate. the method further includes forming a patterned etch mask on the structure, wherein the patterned etch mask provides an opening that is directly above a first fin of the fins, wherein the first fin is directly above the first well region. the method further includes etching the structure through the patterned etch mask, wherein the etching removes the first fin and forms a recess in the substrate that spans from the first well region into the second well region; and forming a dielectric material between remaining portions of the fins and within the recess.
Inventor(s): Ming-Da Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Tzy-Kuang Lee of Taichung (TW) for taiwan semiconductor manufacturing co., ltd., Song-Bor Lee of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Hsiung Lu of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Hao Tsai of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Che Chang of Taichung (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L23/00
CPC Code(s): H01L21/76885
Abstract: a method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. the step comprises a second top surface of the passivation layer. the method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.
Inventor(s): Tefu Yeh of Kaohsiung (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Chieh Tu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hao-Hsin Chen of Keelung (TW) for taiwan semiconductor manufacturing co., ltd., Jo-Chun Hung of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ying-Liang Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Hsi Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Bin Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/775
CPC Code(s): H01L21/823842
Abstract: disclosed is a method of forming gate structures for n-type and p-type transistors. the method includes: forming an interfacial layer and high-k (hk) dielectric layer for the gate structures; forming an n-type metal layer over the hk dielectric layer; forming a hard capping layer over the n-type metal layer while simultaneously strengthening the hk dielectric layer by fluorine passivation; patterning photo resist (pr) material over the hard capping layer that exposes a portion of the hard capping layer over the p-type transistor; removing the n-type metal layer and the hard capping layer over the p-type transistor via wet etching operations using high selectivity chemicals that are highly selective to the hard capping layer and the n-type metal layer; removing the patterned pr material while insulating, by the hard capping layer, gate structures from aluminum oxidation; and forming a p-type metal layer over the hard capping layer and the p-type transistor.
Inventor(s): Cheng-Hung WANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Lin LEE of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Chih CHIANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Jung CHEN of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8249, H01L21/02, H01L21/3065, H01L27/06
CPC Code(s): H01L21/8249
Abstract: disclosed is a method for forming a crystalline protective polysilicon layer which does not create defective voids during subsequent processes so as to provide effective protection to devices underneath. in one embodiment, a method for forming a semiconductor device, includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a second polysilicon layer over the epitaxial layer, wherein the protective coating comprises a third polysilicon layer, wherein the third polysilicon layer is deposited at a first temperature in a range of 600-700 degree celsius, and wherein the third polysilicon layer in the protect coating is configured to protect the first polysilicon layer when the second polysilicon layer is etched.
Inventor(s): Wei-Chih Chen of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Hsun Lee of Hsin-chu County (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Shi Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hao-Cheng Hou of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jung-Wei Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Ding Wang of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Hsiang Hu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Sih-Hao Liao of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/31, H01L21/56, H01L23/16, H01L23/538, H01L25/00, H01L25/065
CPC Code(s): H01L23/3128
Abstract: a package structure and a method of forming the same are provided. the package structure includes a first die, a second die, a first encapsulant, and a buffer layer. the first die and the second die are disposed side by side. the first encapsulant encapsulates the first die and the second die. the second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. the buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. the buffer layer has a young's modulus less than a young's modulus of the first encapsulant and a young's modulus of the second encapsulant.
Inventor(s): Shang-Yun Hou of Jubei (TW) for taiwan semiconductor manufacturing co., ltd., Hsien-Pin Hu of Zhubei (TW) for taiwan semiconductor manufacturing co., ltd., Sao-Ling Chiu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Hsin Wei of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ping-Kang Huang of Chiayi (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Ta Shen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Szu-Wei Lu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ying-Ching Shih of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Chih Chiou of Zhunan Township (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Hsi Wu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/498, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/538
CPC Code(s): H01L23/49816
Abstract: a semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
Inventor(s): Chin-Hua Wang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shu-Shen Yeh of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Chen Lai of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Po-Yao Lin of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/498, H01L23/00, H01L23/14, H01L25/065
CPC Code(s): H01L23/49822
Abstract: some embodiments relate to a semiconductor structure including a substrate with conductive pads and conductive bumps disposed on the conductive pads, respectively. a multi-tiered solder-resist structure includes a first tier and a second tier. the first tier includes a first dielectric material and first conductive bump openings defined by inner sidewalls of the first tier. the first tier has a first width measured through the first dielectric material between the inner sidewalls of the first tier in a cross-sectional view. the second tier overlies the first tier and includes a second dielectric material and second conductive bump openings defined by inner sidewalls of the second tier. the second tier has a second width measured through the second dielectric material between the inner sidewalls of the second tier in the cross-sectional view. a ratio of the first width to the second width ranges from 1.1:1 to 2:1.
Inventor(s): Kam-Tou Sio of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Jiann-Tyng Tzeng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L21/02, H01L21/8238, H01L23/528, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L23/5223
Abstract: a semiconductor device includes a substrate having a first side and a second side; an active region arranged on the first side, and extending along a first lateral direction; a first gate structure arranged on the first side, extending along a second lateral direction perpendicular to the first lateral direction, disposed over the active region, and wrapping a first portion of the active region; a first interconnecting structure arranged on the first side, electrically coupled to the first gate structure, and disposed over the first gate structure; and a second interconnecting structure arranged on the second side, and electrically coupled to one or more portions of the active region. the active region, the first gate structure, the first interconnecting structure, and the second interconnecting structure are collectively configured as a decoupling capacitor.
Inventor(s): Guo-Huei Wu of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Hui-Zhong Zhuang of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Liang Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shang-Wen Chang of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsun Chiu of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528
CPC Code(s): H01L23/5226
Abstract: a semiconductor device includes a first gate structure extending along a first lateral direction. the semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. the first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. the semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. the second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.
20240222281. INTEGRATED CIRCUIT_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Shih-Wei PENG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Tien WU of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Jiann-Tyng TZENG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/538, H01L21/768
CPC Code(s): H01L23/5384
Abstract: an integrated circuit includes conductive rails that are disposed in a first conductive layer and separated from each other in a layout view, signal rails disposed in a second conductive layer different from the first conductive layer, at least one first via coupling a first signal rail of the signal rails to at least one of the conductive rails, and at least one first conductive segment. the first signal rail transmits a supply signal through the at least one first via and the at least one of the conductive rails to at least one element of the integrated circuit. the at least one first via and the at least one first conductive segment are disposed above first conductive layer. the at least one first conductive segment is coupled to the at least one of the conductive rails and is separate from the first signal rail.
Inventor(s): Wei-Cheng Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Chia Chiu of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Hsien Hsieh of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Li-Han Hsu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd., Meng-Tsan Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Shu Lin of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/552, H01L21/56, H01L21/768, H01L23/00, H01L23/31, H01L23/488, H01L23/538
CPC Code(s): H01L23/552
Abstract: a semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. the redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. the first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. the connective terminals include dummy connective terminals and active connective terminals. the dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. the active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. vertical projections of the dummy connective terminals fall on the shielding plate.
Inventor(s): Hsien-Ju Tsou of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Chi Lin of Su-Lin City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsiu Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tsang-Jiuh Wu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L21/304, H01L21/3065
CPC Code(s): H01L23/562
Abstract: in an embodiment, a device includes an integrated circuit die including a first sidewall, a second sidewall, and a third sidewall, wherein the third sidewall of the integrated circuit die is connected to the first sidewall of the integrated circuit die and the second sidewall of the integrated circuit die, wherein the third sidewall of the integrated circuit die forms a chamfered corner of the integrated circuit die; a first dielectric surrounding the integrated circuit die; a semiconductor feature disposed over the integrated circuit die, wherein the semiconductor feature includes a first sidewall, a second sidewall, and a third sidewall, wherein the third sidewall of the semiconductor feature is connected to the first sidewall of the semiconductor feature and the second sidewall of the semiconductor feature and forms a chamfered corner of the semiconductor feature; and a second dielectric surrounding the semiconductor feature.
Inventor(s): Chien-Hsun Chen of Zhutian Township (TW) for taiwan semiconductor manufacturing co., ltd., Shou-Yi Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jiun Yi Wu of Zhongli City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Shi Liu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/683, H01L23/31, H01L23/498, H01L23/538, H01L23/66, H01L25/18
CPC Code(s): H01L24/24
Abstract: in an embodiment, a device includes: a semiconductor device; and a redistribution structure including: a first dielectric layer; a first grounding feature on the first dielectric layer; a second grounding feature on the first dielectric layer; a first pair of transmission lines on the first dielectric layer, the first pair of transmission lines being laterally disposed between the first grounding feature and the second grounding feature, the first pair of transmission lines being electrically coupled to the semiconductor device; a second dielectric layer on the first grounding feature, the second grounding feature, and the first pair of transmission lines; and a third grounding feature extending laterally along and through the second dielectric layer, the third grounding feature being physically and electrically coupled to the first grounding feature and the second grounding feature, where the first pair of transmission lines extend continuously along a length of the third grounding feature.
Inventor(s): Kai Jun ZHAN of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chang-Jung HSUEH of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hui-Min HUANG of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Hung LIN of Xinfeng Township (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Da CHENG of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/75
Abstract: a method for forming a package structure is provided. the method includes transporting a first package component into a processing chamber. the method includes positioning the first package component on a chuck table. the method includes using the chuck table to heat the first package component. the method includes holding a second package component with a bonding head. the bonding head communicates with a plurality of vacuum devices via a plurality of vacuum tubes, and the vacuum devices each operate independently. the method also includes bonding the first package component and the second package component in the processing chamber to form the package structure.
Inventor(s): Jing-Cheng LIN of Chu Tung Zhen (TW) for taiwan semiconductor manufacturing co., ltd., Po-Hao TSAI of Zhongli City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, B23K1/00, H01L21/768, H01L23/498, B23K101/42
CPC Code(s): H01L24/83
Abstract: a method of making a semiconductor device includes patterning a photoresist on a substrate to form a plurality of openings. a first opening has a first width, a second opening has a second width, smaller than the first width, and a third opening is between the first opening and the second opening and has a third width, different from the first width and the second width. the width is measured in a direction parallel to a top surface of the substrate. the method further includes plating a first conductive material into each opening of the plurality of openings in the photoresist. plating the first conductive material includes plating of the first conductive material to a first height in the first opening, plating the first conductive material to a second height in the second opening, and plating the first conductive material to a third height in the third opening.
Inventor(s): Kuo-Chiang Ting of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ta Hao Sung of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/10, H01L21/56, H01L23/00, H01L23/31, H01L25/00, H01L25/18, H10B80/00
CPC Code(s): H01L25/105
Abstract: in an embodiment, a device includes a first integrated circuit die, wherein the first integrated circuit die includes a substrate formed of a semiconductor material and a conductive via penetrating through the substrate; a second integrated circuit die disposed laterally adjacent to the first integrated circuit die; a first gap-filling layer disposed between the first integrated circuit die and the second integrated circuit die, wherein the first gap-filling layer is formed of a material selected from silicon, silicon carbide, silicon oxynitride, silicon nitride, the semiconductor material of the substrate, or a combination thereof; and a third integrated circuit die attached to the first integrated circuit die in a face-to-back manner.
Inventor(s): Po-Lin PENG of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Li-Wei CHU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Fu TSAI of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jam-Wem LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ti SU of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/02, H01L23/60, H01L23/62, H01L27/06, H01L29/08, H01L29/10, H01L29/747, H01L29/861, H01L29/87
CPC Code(s): H01L27/0262
Abstract: a semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. the first diode is coupled between an input/output (i/o) pad and a first voltage terminal. the second diode is coupled with the first diode, the i/o pad and a second voltage terminal. the clamp circuit is coupled between the first voltage terminal and the second voltage terminal. the second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (esd) current flowing between the i/o pad and the first voltage terminal. the third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the esd current flowing between the i/o pad and the first voltage terminal.
Inventor(s): Tao-Yi HUNG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jam-Wem LEE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Ji CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wun-Jie LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/02, H01L21/8234, H01L23/528
CPC Code(s): H01L27/0266
Abstract: an integrated circuit (ic) device includes an antenna effect protection device, and a to-be-protected device. a first source/drain of the antenna effect protection device is electrically coupled to a first conductor configured to carry a reference voltage. a second source/drain of the antenna effect protection device is electrically coupled by a second conductor to a gate of the to-be-protected device. the antenna effect protection device is a bulk-less device.
Inventor(s): Che-Chia HSU of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Pin TSAO of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hong HWANG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Hsun CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L27/0924
Abstract: a semiconductor device includes a plurality of nanostructures over a substrate arranged in a z-axis and a gate stack wrapping around the plurality of nanostructures. thea gate stack comprises a gate dielectric layer and a p-type work function material on the gate dielectric layer. the gate dielectric layer wraps around the plurality of nanostructures. the p-type work function material has a first thickness along the z-axis above a topmost one of the plurality of nanostructures and a second thickness along the z-axis between neighboring two of the plurality of nanostructures, and the first thickness is less than the second thickness.
Inventor(s): Min-Feng Kao of Chiayi City (TW) for taiwan semiconductor manufacturing co., ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Chang Kuo of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Chau Chen of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Chi Hung of Chu-Bei City (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Chan Li of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/1463
Abstract: some embodiments relate to an image sensor. the image sensor includes a semiconductor substrate including a pixel region and a peripheral region. a backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. the backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. a conductive feature is disposed over a front side of the semiconductor substrate. a through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. the through substrate via is laterally offset from the backside isolation structure. a conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.
Inventor(s): Yu-Lien Huang of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Guan-Ren Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Feng Fu of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/764, H01L21/8238, H01L27/092, H01L29/08, H01L29/417, H10B10/00
CPC Code(s): H01L29/0649
Abstract: in an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ild) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ild layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ild layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.
Inventor(s): Marcus Johannes Henricus Van Dal of Linden (BE) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/8238, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a method of forming a semiconductor structure is provided. a complementary fet (cfet) device including a first fet device and a second fet device isolated with each other by a middle dielectric layer is formed. the first and second fet devices are stacked over each other in a vertical direction. a first inner spacer is formed immediately below and above a peripheral portion of each of a plurality of first nanosheet channels of the first fet device. a second inner spacer is formed immediately below and above a peripheral portion of each of a plurality of second nanosheet channels of the second fet device. the first inner spacers and the second inner spacers are formed at different process steps.
Inventor(s): Huang-Chao CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Sheng LIANG of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Jhon Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/417, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a semiconductor device includes a dielectric wall, an isolation structure, first and second semiconductor channels, and a gate structure. the dielectric wall is on a substrate and extending along a first direction from a top view. the isolation structure is in the substrate and having a top surface lower than that of the dielectric wall. the first and second semiconductor channels are respectively on opposite first and second sides of the dielectric wall. the gate structure extends across the first and second semiconductor channels along a second direction different from the first direction from the top view. from the top view the gate structure comprises a first profile over the first semiconductor channels and a second profile over the isolation structure, the first profile has a first width at the first side of the dielectric wall, and the first width is greater than a width of the second profile.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsien CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi HUANG of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Pin TSAO of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Sheng LIANG of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao CHANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/417, H01L29/66, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a method of forming a semiconductor device includes the following steps. a substrate is patterned to form a fin structure. the fin structure is recessed to form a recess in the fin structure. an epitaxial source/drain region is grown from the recess. a first silicide layer is formed on the epitaxial source/drain region. a first portion of the first silicide layer is thinned, while leaving a second portion of the first silicide layer un-thinned. a metal contact is formed in contact with the thinned first portion of the first silicide layer.
Inventor(s): Jia-Heng WANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Pang-Chi WU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chao-Hsun WANG of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Fu-Kai YANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Mei-Yun WANG of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/8234
CPC Code(s): H01L29/0673
Abstract: semiconductor structures and methods for manufacturing the same are provided. the semiconductor structure includes nanostructures spaced apart from each other in a first direction and a gate structure formed over and around the nanostructures. the semiconductor structure further includes a gate spacer covering a sidewall of the gate structure and a source/drain structure attached to the nanostructures in a second direction. the semiconductor structure further includes a contact spaced apart from the gate structure by the gate spacer in the second direction and a first conductive structure landing over the gate structure. the semiconductor structure further includes a second conductive structure formed over the gate spacer. in addition, a portion of the second conductive structure is sandwiched between the first conductive structure and the contact.
Inventor(s): Feng-Ming CHANG of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/08, H01L21/8234, H01L29/06, H01L29/423, H01L29/786
CPC Code(s): H01L29/0847
Abstract: a method for forming a semiconductor device structure is provided. the method includes forming a gate stack, a first source/drain structure and a second source/drain structure over a front surface of a substrate. the gate stack is between the first source/drain structure and the second source/drain structure. the method includes removing a first portion of the substrate from a back surface of the substrate to form a through hole in the substrate. the through hole passes through the substrate and exposes a second portion of the first source/drain structure. the method includes forming a semiconductor structure in the through hole. the method includes forming a silicide layer in the through hole and over the semiconductor structure. the method includes forming a contact structure in the through hole and over the silicide layer.
Inventor(s): Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L29/06, H01L29/08, H01L29/40, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L29/41733
Abstract: a method for manufacturing a semiconductor structure includes forming a fin over a substrate in a z-direction. the fin includes first semiconductor layers and second semiconductor layers alternating stacked. the method further includes forming a dummy gate structure extending in a y-direction and over the fin, forming a first source/drain feature and a second source/drain feature on opposite sides of the dummy gate structure in an x-direction, removing the dummy gate structure and the first semiconductor layers in the fin to form a gate trench, and forming a gate structure in the gate trench. the gate structure wraps around the second semiconductor layers. the method further includes forming a via in contact with a bottom surface of the first source/drain feature. the bottom surface of the first source/drain feature is lower than a bottom surface of the second source/drain feature.
Inventor(s): Hsin-Fu LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Ta HSIEH of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Hao YEH of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L29/40, H01L29/66, H01L29/78
CPC Code(s): H01L29/42368
Abstract: a semiconductor device includes a semiconductor layer and a gate structure on the semiconductor layer. the gate structure includes a multi-stepped gate dielectric on the semiconductor layer and a gate electrode on the multi-stepped gate dielectric. the multi-stepped gate dielectric includes a first gate dielectric segment having a first thickness and a second gate dielectric segment having a second thickness that is less than the first thickness.
Inventor(s): Jia-Chuan YOU of Taoyuan County (TW) for taiwan semiconductor manufacturing co., ltd., Huan-Chieh SU of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng CHIANG of Zhubei City, Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Baoshan Township, Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L27/088, H01L29/66, H01L29/78
CPC Code(s): H01L29/42376
Abstract: a semiconductor device structure includes a first channel structure and a second channel structure over a substrate. the semiconductor device structure also includes a first gate stack over the first channel structure and a second gate stack over the second channel structure. the first gate stack and the second gate stack have a first work function layer and a second work function layer, respectively. the first work function layer and the second work function layer are made of a same material. the second gate stack has a first protruding portion and a second protruding portion, and each of the first protruding portion and the second protruding portion extends upwards and extend away from the second channel structure. the first protruding portion and the second protruding portion are spaced apart from each other, and half of the first gate stack is wider than the first protruding portion.
Inventor(s): Chih-Yang CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L29/08
CPC Code(s): H01L29/42392
Abstract: a method includes forming first and second semiconductor layers, in which a number of the first semiconductor layers is less than a number of the second semiconductor layers.
Inventor(s): Chih-Yang CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L29/08
CPC Code(s): H01L29/42392
Abstract: embodiments includes etching first and second semiconductor layers to form a first recess within the first semiconductor layers and a second recess within the second semiconductor layers; performing an etching process to deepen the second recess; and forming a first and second source/drain epitaxy structures in the first recess and the deepened second recess. embodiments also includes after the first and second recesses are formed, performing a first deposition process to form first and second epitaxy layers in the first and second recesses, respectively; performing a second deposition process to form a third epitaxy layer over the first epitaxy layer; and performing a third deposition process to form fourth and fifth epitaxy layers over the third and second epitaxy layers, respectively.
Inventor(s): Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L23/522, H01L29/06, H01L29/08, H01L29/786
CPC Code(s): H01L29/42392
Abstract: a method for forming a semiconductor structure is provided. the method includes forming an active region over a substrate. the active region includes a fin element and a plurality of first semiconductor layers and a plurality of second semiconductor layers which are alternately stacked over the fin element. the plurality of first semiconductor layers includes a lowermost first semiconductor layer, and the lowermost first semiconductor layer is thicker than other first semiconductor layers. the method further includes etching the active region to form a first source/drain recess, forming a dielectric isolation feature in the first source/drain recess, forming a first source/drain feature over the dielectric isolation feature in the first source/drain recess, removing the plurality of first semiconductor layers, and forming a gate stack surrounding the second semiconductor layers.
Inventor(s): Li-Zhen YU of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Shih-Chuan CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Lin-Yu HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Chi CHUANG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., CHIH-HAO WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Huan-Chieh SU of Changhua (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/8238, H01L27/088, H01L29/417, H01L29/49, H01L29/66
CPC Code(s): H01L29/785
Abstract: a semiconductor device structure includes a source/drain (s/d) feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. the structure also includes a first silicide layer in contact with the first surface of the s/d feature, a second silicide layer opposing the first silicide layer and in contact with the second surface of the s/d feature, a front side s/d contact in contact with the first silicide layer, a back side s/d contact in contact with the second silicide layer, a semiconductor channel layer comprising a sidewall in contact with the sidewall of the source/drain feature, a gate dielectric layer surrounding exposed surfaces of the semiconductor layer, an interlayer dielectric (ild) disposed adjacent to the gate dielectric layer, and a liner disposed between and in contact with the ild and the gate dielectric layer.
Inventor(s): Shi Ning JU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng CHIANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Lun CHENG of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/762, H01L21/768, H01L21/8234, H01L21/8238, H01L23/522, H01L23/528, H01L27/088, H01L27/092, H01L29/417, H01L29/66
CPC Code(s): H01L29/7851
Abstract: a semiconductor structure includes a power rail on a back side of the semiconductor structure, a first interconnect structure on a front side of the semiconductor structure, and a source feature, a drain feature, a first semiconductor fin, and a gate structure that are between the power rail and the first interconnect structure. the first semiconductor fin connects the source feature and the drain feature. the gate structure is disposed on a front surface and two side surfaces of the first semiconductor fin. the semiconductor structure further includes an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin and a via penetrating through the isolation structure and connecting the source feature to the power rail.
Inventor(s): Chu Fu CHEN of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Feng HUANG of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Chung CHEN of Keelung (TW) for taiwan semiconductor manufacturing co., ltd., Chin-Lung CHEN of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Victor Chiang LIANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Cheng PAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H02M3/158, H01L21/84, H01L29/08, H01L29/423, H01L29/66, H01L29/78, H01L29/80, H01L21/265
CPC Code(s): H02M3/1582
Abstract: a method of making a semiconductor device includes implanting a source/drain (s/d) in the substrate adjacent to a gate structure. the method further includes implanting a lightly doped drain (ldd) region in the substrate in direct contact with the s/d, wherein a dopant concentration in the ldd region is less than a dopant concentration in the s/d. the method further includes implanting a doping extension region in the substrate in direct contact with the ldd region, wherein a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the ldd.
Inventor(s): Hung-Chih Ou of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Hao Chen of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03K3/012, H03K17/56
CPC Code(s): H03K3/012
Abstract: a device including a first supply voltage track, a second supply voltage track, a first reference track, a first standard cell, and a second standard cell. the first supply voltage track is configured to provide a first voltage and the second supply voltage track is configured to provide a second voltage that is greater than the first voltage. the first standard cell is configured to be electrically connected to the first supply voltage track to receive the first voltage and electrically connected to the first reference track. the second standard cell is configured to be electrically connected to the second supply voltage track to receive the second voltage and electrically connected to the first reference track.
Inventor(s): Yueh CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Shang-Hsuan CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Xiang LU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuang-Ching CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03K3/3562, H01L27/02, H01L27/092, H03K3/356, H03K19/20
CPC Code(s): H03K3/35625
Abstract: a flip-flop includes a first input circuit, a first nor logic gate, a stacked gate circuit, a first nand logic gate and an output circuit. the first input circuit generates a first signal responsive to at least a first data signal, a first or a second clock signal. the first nor logic gate is coupled between a first and a second node, and generates a second signal responsive to the first signal and a first reset signal. the stacked gate circuit is coupled between the first and a third node, and generates a third signal responsive to the first signal. the first nand logic gate is coupled between the third and a fourth node, and generates a fourth signal responsive to the third signal and a second reset signal. the output circuit is coupled to the fourth node, and generates a first output signal responsive to the fourth signal.
Inventor(s): Chaitanya Palusa of San Jose CA (US) for taiwan semiconductor manufacturing co., ltd., Rob Abbott of Ontario (CA) for taiwan semiconductor manufacturing co., ltd., Wei-Li Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Po-Hsiang Lan of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Dirk Pfaff of Ontario (CA) for taiwan semiconductor manufacturing co., ltd., Cheng-Hsiang Hsieh of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H04L25/03, H03K5/00, H03K5/135, H04L25/02, H04L27/01
CPC Code(s): H04L25/03878
Abstract: a multi-tap differential feedforward equalizer (dffe) configuration with both precursor and postcursor taps is provided. the dffe has reduced noise and/or crosstalk characteristics when compared to a feedforward equalizer (ffe) since dffe uses decision outputs of slicers as inputs to a finite impulse response (fir) unlike ffe which uses actual analog signal inputs. the digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. the decisions at the outputs of the tentative decision slicers are tentative and are used in a fir filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. the bit-error-rate (ber) of the final stage decisions are lower or better than the ber of the previous stage tentative decisions.
Inventor(s): Ming-Heng TSAI of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Sheng LIANG of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jhon Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B10/00, G11C11/412
CPC Code(s): H10B10/12
Abstract: a device includes a first transistor, a second transistor, and a dielectric wall. the first transistor includes first semiconductor channel layers, a first gate structure, and first source/drain structures on opposite sides of the first gate structure. the second transistor includes second semiconductor channel layers, a second gate structure, and second source/drain structures on opposite sides of the second gate structure. the dielectric wall includes a first sidewall abutting side surfaces of the first semiconductor channel layers in a first cross-sectional view taken along a longitudinal axis of the first gate structure, the first sidewall of the dielectric wall also abutting side surfaces of second semiconductor channel layers in a second cross-sectional view taken along a longitudinal axis of the second gate structure, in which in a top view, the first sidewall of the dielectric wall has a stepped profile.
20240224489. SEMICONDUCTOR DEVICE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/125
Abstract: semiconductor devices with dual-port memory cells are provided. first inverter includes first pull-up transistor, and first and second pull-down transistors connected in parallel. second inverter includes second pull-up transistor, and third and fourth pull-down transistors connected in parallel. first and second pass-gate transistors are coupled to the first inverter to form a first port. third and fourth pass-gate transistors are coupled to the second inverter to form a second port. first and second pass-gate transistors and the first and third pull-down transistors share first continuous active region. the third and fourth pass-gate transistors and the second and fourth pull-down transistors share a second continuous active region. the first and second pull-up transistors and first and second isolation transistors share a third continuous active region. gates of the first and second isolation transistors are electrically connected to vdd line. sources of the first and second isolation transistors are floating.
Inventor(s): Meng-Sheng Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chia-En Huang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B20/20
CPC Code(s): H10B20/20
Abstract: an otp memory cell is provided. the otp memory cell includes: an antifuse transistor, wherein a gate terminal of the antifuse transistor is connected to a first word line having a first signal, and the antifuse transistor is selectable between a first state and a second state in response to the first signal; and a selection transistor connected between the antifuse transistor and a bit line, wherein a gate terminal of the selection transistor is connected to a second word line having a second signal, and the selection transistor is configured to provide access to the antifuse transistor in response to the second signal. a first terminal of the antifuse transistor is a vacancy terminal, and a second terminal of the antifuse transistor is connected to the selection transistor.
Inventor(s): Yun-Feng Kao of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Katherine H CHIANG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B51/40, G11C11/22, H01L29/417, H01L29/423, H01L29/51, H01L29/78, H10B51/30, H03K19/20, H10B51/10
CPC Code(s): H10B51/40
Abstract: an active device, a semiconductor device and a logic gate are provided. the active device includes: a channel layer; a top source/drain electrode, disposed at a top side of the channel layer; a first bottom source/drain electrode and a second bottom source/drain electrode, disposed at a bottom side of the channel layer; a first gate structure and a second gate structure, located between the top source/drain electrode and the first bottom source/drain electrode, wherein the first gate structure comprises a non-ferroelectric dielectric layer, and the second gate structure comprises a ferroelectric layer; and a third gate structure and a fourth gate structure, located between the top source/drain electrode and the second bottom source/drain electrode, wherein the third gate structure comprises a non-ferroelectric dielectric layer, and the fourth gate structure comprises a ferroelectric layer.
20240224813. MRAM CELL AND MRAM_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Perng-Fei YUH of Walnut Creek CA (US) for taiwan semiconductor manufacturing co., ltd., Yih WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N50/80, G11C5/02, G11C11/16, H10B61/00
CPC Code(s): H10N50/80
Abstract: magnetic random access memory (mram) cells are provided. mram cell includes a plurality of stacked magnetic tunnel junction (mtj) devices coupled in serial and coupled between a bit line and a source line. the stacked mtj devices have different sizes. each of the stacked mtj devices includes a free layer, a pinned layer and a barrier layer between the free layer and the pinned layer. the free layers of two adjacent stacked mtj devices are in direct contact with each other.
20240224822. RRAM STRUCTURE_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Hai-Dang Trinh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chii-Ming Wu of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Hsing-Lien Lin of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Fa-Shen Jiang of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10N70/00, H01L23/528, H10B63/00, H10N70/20
CPC Code(s): H10N70/841
Abstract: in some embodiments, the present disclosure relates to an integrated chip. the integrated chip includes a bottom electrode structure disposed over a lower interconnect within a lower inter-level dielectric (ild) layer over a substrate. the bottom electrode structure has an upper surface including a noble metal. a diffusion barrier layer is over the bottom electrode structure, a data storage structure is over the diffusion barrier layer, and a top electrode structure is over the data storage structure. the diffusion barrier layer is configured to mitigate a diffusion of noble metal atoms from the bottom electrode structure to the data storage structure.
Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on July 4th, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- B24B37/005
- B24B51/00
- H01L21/67
- CPC B24B37/005
- Taiwan semiconductor manufacturing co., ltd.
- B24B37/10
- B24B37/04
- B24B49/00
- H01L21/306
- CPC B24B37/107
- G02B6/12
- G02B6/122
- G02B6/13
- G06N3/067
- CPC G02B6/12002
- G02B6/125
- CPC G02B6/1228
- G05F1/46
- H03K5/003
- CPC G05F1/46
- G11C11/408
- G11C11/4076
- G11C11/4093
- H03K19/20
- CPC G11C11/4087
- G11C29/42
- G11C29/20
- G11C29/24
- G11C29/44
- CPC G11C29/42
- H01F21/12
- CPC H01F21/12
- H01J37/305
- H01J37/08
- CPC H01J37/3053
- H01J37/32
- C23C16/458
- H01L21/66
- H01L21/677
- CPC H01J37/3288
- H01L21/02
- H01L21/768
- H01L27/088
- H01L29/66
- CPC H01L21/02175
- H01L21/027
- H01L21/033
- CPC H01L21/0274
- G03F7/00
- G03F7/16
- H01L21/687
- H01L21/311
- CPC H01L21/31144
- H01L21/762
- H01L21/3065
- H10B10/00
- CPC H01L21/76224
- H01L23/00
- CPC H01L21/76885
- H01L21/8238
- H01L27/092
- H01L29/06
- H01L29/423
- H01L29/775
- CPC H01L21/823842
- H01L21/8249
- H01L27/06
- CPC H01L21/8249
- H01L23/31
- H01L21/56
- H01L23/16
- H01L23/538
- H01L25/00
- H01L25/065
- CPC H01L23/3128
- H01L23/498
- H01L21/48
- CPC H01L23/49816
- H01L23/14
- CPC H01L23/49822
- H01L23/522
- H01L23/528
- H01L29/786
- CPC H01L23/5223
- CPC H01L23/5226
- CPC H01L23/5384
- H01L23/552
- H01L23/488
- CPC H01L23/552
- H01L21/304
- CPC H01L23/562
- H01L21/683
- H01L23/66
- H01L25/18
- CPC H01L24/24
- CPC H01L24/75
- B23K1/00
- B23K101/42
- CPC H01L24/83
- H01L25/10
- H10B80/00
- CPC H01L25/105
- H01L27/02
- H01L23/60
- H01L23/62
- H01L29/08
- H01L29/10
- H01L29/747
- H01L29/861
- H01L29/87
- CPC H01L27/0262
- H01L21/8234
- CPC H01L27/0266
- CPC H01L27/0924
- H01L27/146
- CPC H01L27/1463
- H01L21/764
- H01L29/417
- CPC H01L29/0649
- CPC H01L29/0673
- CPC H01L29/0847
- H01L29/40
- CPC H01L29/41733
- H01L29/78
- CPC H01L29/42368
- CPC H01L29/42376
- CPC H01L29/42392
- H01L29/49
- CPC H01L29/785
- CPC H01L29/7851
- H02M3/158
- H01L21/84
- H01L29/80
- H01L21/265
- CPC H02M3/1582
- H03K3/012
- H03K17/56
- CPC H03K3/012
- H03K3/3562
- H03K3/356
- CPC H03K3/35625
- H04L25/03
- H03K5/00
- H03K5/135
- H04L25/02
- H04L27/01
- CPC H04L25/03878
- G11C11/412
- CPC H10B10/12
- CPC H10B10/125
- H10B20/20
- CPC H10B20/20
- H10B51/40
- G11C11/22
- H01L29/51
- H10B51/30
- H10B51/10
- CPC H10B51/40
- H10N50/80
- G11C5/02
- G11C11/16
- H10B61/00
- CPC H10N50/80
- H10N70/00
- H10B63/00
- H10N70/20
- CPC H10N70/841
