Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on July 25th, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd. on July 25th, 2024
Taiwan Semiconductor Manufacturing Co., Ltd.: 74 patent applications
Taiwan Semiconductor Manufacturing Co., Ltd. has applied for patents in the areas of H01L29/66 (31), H01L29/78 (23), H01L29/06 (18), H01L29/423 (16), H01L21/02 (12) H01L29/66795 (2), H01L23/5286 (2), H01L23/5226 (2), H01L29/0649 (2), H01L29/0673 (2)
With keywords such as: layer, structure, semiconductor, gate, dielectric, region, substrate, device, forming, and source in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s): Wei Chang CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Kuang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Hung LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): B08B9/04, C23C16/44, H01L21/67
CPC Code(s): B08B9/04
Abstract: embodiments of the present disclosure relate to apparatus and methods for cleaning an exhaust path of a semiconductor process tool. one embodiment provides an exhaust pipe section and a pipe cleaning assembly connected between a semiconductor process tool and a factory exhaust. the pipe cleaning assembly includes a residue remover disposed in the exhaust pipe section. the residue remover is operable to move in the exhaust pipe section to dislodge accumulated materials from an inner surface of the exhaust pipe section.
Inventor(s): Yi-Chen HO of Taichung (TW) for taiwan semiconductor manufacturing co., ltd., Chih Ping LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chien Ting LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jie-Ying YANG of Yunlin County (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Ming WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Ker-Hsun LIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Hsun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): F16F7/10
CPC Code(s): F16F7/10
Abstract: a method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.
Inventor(s): Lan-Chou CHO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Stefan RUSU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G02B6/12, G02B6/136
CPC Code(s): G02B6/12004
Abstract: a photonic system includes a waveguide. the photonic system further includes a micro ring modulator (mrm) spaced from the waveguide. the photonic system further includes a heater configured to increase a temperature of the mrm in response to the heater receiving a first voltage. the photonic system further includes a cooling element configured to decrease a temperature of the mrm in response to the cooling element receiving a second voltage.
Inventor(s): Sheng-Min WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ken-Hsien HSIEH of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Manuel Alejandro Fernandez LOPEZ of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Tse LAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F1/22, G03F1/52, G03F1/80, G03F7/20
CPC Code(s): G03F1/22
Abstract: a first bright field reticle and a second bright field reticle are utilized for a double exposure euv photolithography process in which exposure areas of the first and second bright field reticles overlap. the first and second reticles each include, respectively, a substrate, a reflective multilayer on the substrate, a main pattern of absorption material on the reflective multilayer, a black border area, and an additional absorption area of the absorption material between the black border and the main pattern.
Inventor(s): Chansyun David YANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Keh-Jeng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chan-Lon YANG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G03F7/00
CPC Code(s): G03F7/70033
Abstract: a method for generating an extreme ultraviolet (euv) radiation includes simultaneously irradiating two or more target droplets with laser light in an euv radiation source apparatus to produce euv radiation and collecting and directing the euv radiation produced from the two or more target droplet by an imaging mirror.
Inventor(s): Yen-An Chang of Miaoli County (TW) for taiwan semiconductor manufacturing co., ltd., Po-Hao Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Chun Shih of Taipei (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C11/16
CPC Code(s): G11C11/1697
Abstract: the disclosed system and method reduce on-chip power ir drop caused by large write current, to increase the write io number or improve write throughput and to suppress write voltage ripple at the start and end of a write operation. the disclosed systems and methods are described in relation to stabilizing the bit line voltage for mrams, however, the disclosed systems and methods can be used to stabilize the bit line voltage of any memory configuration that draws large currents during short write pulses or, more generally, to selectively assist a power supply generator in supplying adequate power to a load at times of large power consumption.
Inventor(s): Chung-Chieh Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Hsiung Kuo of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Der Chih of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C16/28, G11C16/10, H03K19/20
CPC Code(s): G11C16/28
Abstract: a sense amplifier control system includes a precharge control switch configured to receive a precharge signal. a reference cell is configured to receive a reference word line signal. in a precharge phase, the control switch is controlled in response to the precharge signal to precharge the reference input node to a predetermined precharge level. in a sensing phase subsequent to the pre-charge phase, the trigger circuit is configured to output a triggering signal at the output terminal in response to the reference input node reaching a triggering level.
Inventor(s): Perng-Fei Yuh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tung-Cheng Chang of Xihu Township (TW) for taiwan semiconductor manufacturing co., ltd., Gu-Huan Li of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-En Huang of Xinfeng Township (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Ying Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yih Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C17/16, G11C17/18, H10B20/20
CPC Code(s): G11C17/16
Abstract: a memory device and a method of operating a memory device are disclosed. in one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. the first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.
Inventor(s): Perng-Fei Yuh of Walnut Creek CA (US) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): G11C17/16, G11C17/18
CPC Code(s): G11C17/16
Abstract: in some aspects of the present disclosure, a memory array includes: a plurality of memory cells; and a plurality of logic gates, each of the plurality of logic gates having a first input, a second input, and an output gating a corresponding one of the plurality of memory cells, wherein the first input of each of the plurality of logic gates of a first subset is coupled to a first bit select line.
Inventor(s): Po-Tang TSENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Heng YEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tai-Kun KAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Tai PENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chun Yan CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01J37/08, H01J37/317
CPC Code(s): H01J37/08
Abstract: an ion source head includes a curved liner that is configured to more closely and accurately repel, direct, or deflect ion species generated within an ion source cavity of an ion source container of an ion source head towards an ion beam opening that extends through the ion source container of the ion source head. this prevents or reduces the ion species from becoming trapped in the ion source cavity instead of exiting the ion source cavity through the ion beam opening that extends through the ion source container of the ion source head. the curved liner may be received by a curved structure of the ion source container of the ion source head. the ion source head may be utilized within an implanter tool to refine or process a solid target with the ion beam generated by the ion source head with the curved liner.
Inventor(s): Hsin-Yi Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jia-Ming Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kun-Yu Lee of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/02
CPC Code(s): H01L21/02603
Abstract: a method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (cvd); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. the method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.
Inventor(s): Jing Hong HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Han LAI of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Yu CHANG of Yuansun Village (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/027, G03F7/16, H01L21/033, H01L21/311, H01L21/3213, H01L21/768, H01L21/8238
CPC Code(s): H01L21/0276
Abstract: method of manufacturing semiconductor device, includes forming protective layer over substrate having plurality of protrusions and recesses. the protective layer includes polymer composition including polymer having repeating units of one or more of:
Inventor(s): Jing Hong HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Han LAI of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Yu CHANG of Yuansun Village (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/027, G03F7/16, H01L21/033, H01L21/311, H01L21/3213, H01L21/768, H01L21/8238
CPC Code(s): H01L21/0276
Abstract:
Inventor(s): Jing Hong HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Han LAI of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Ching-Yu CHANG of Yuansun Village (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/027, G03F7/16, H01L21/033, H01L21/311, H01L21/3213, H01L21/768, H01L21/8238
CPC Code(s): H01L21/0276
Abstract: wherein a, b, c, d, e, f, g, h, and i are each independently h, —oh, —roh, —r(oh), —nh, —nhr, —nr, —sh, —rsh, or —r(sh), wherein at least one of a, b, c, d, e, f, g, h, and i on each repeating unit is not h. r, r, and rare each independently a c1-c10 alkyl group, a c3-c10 cycloalkyl group, a c1-c10 hydroxyalkyl group, a c2-c10 alkoxy group, a c2-c10 alkoxy alkyl group, a c2-c10 acetyl group, a c3-c10 acetylalkyl group, a c1-c10 carboxyl group, a c2-c10 alkyl carboxyl group, or a c4-c10 cycloalkyl carboxyl group, and n is 2-1000. a resist layer is formed over protective layer, and resist layer is patterned.
Inventor(s): Ching-Yu Chang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Jung-Hau Shiu of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Jen Hung Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/033, H01L21/02, H01L21/311, H01L21/3213
CPC Code(s): H01L21/0331
Abstract: a method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. the first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material.
Inventor(s): Cheng-Ming LIN of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Yen WOON of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Szuya LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/225, H01L21/22, H01L21/8238, H01L27/092, H01L29/423, H01L29/66, H01L29/78, H01L29/786
CPC Code(s): H01L21/225
Abstract: dipole engineering techniques for devices of stacked device structures are disclosed herein. an exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming an n-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives an n-dipole dopant from the n-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the n-dipole dopant source layer. a drive-in temperature of the thermal drive-in process is less than 600� c. (e.g., about 300� c. to about 500� c.). the n-dipole dopant is strontium, erbium, magnesium, or a combination thereof. the method can further include tuning thermal drive-in process parameters to provide the gate dielectric with an n-dipole dopant profile having a peak located at a high-k/interfacial interface �0.5 nm.
Inventor(s): Sih-Jie Liu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Feng Nieh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Huicheng Chang of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/265, H01L21/266, H01L21/28, H01L21/8238, H01L27/092, H01L29/66, H01L29/78, H10B10/00
CPC Code(s): H01L21/26513
Abstract: a method of forming a semiconductor device includes performing a first implantation process on a semiconductor substrate to form a deep p-well region, performing a second implantation process on the semiconductor substrate with a diffusion-retarding element to form a co-implantation region, and performing a third implantation process on the semiconductor substrate to form a shallow p-well region over the deep p-well region. the co-implantation region is spaced apart from a top surface of the semiconductor substrate by a portion of the shallow p-well region, and the deep p-well region and the shallow p-well region are joined with each other. an n-type fin field-effect transistor (finfet) is formed, with the deep p-well region and the shallow p-well region acting as a well region of the n-type finfet.
Inventor(s): Yu-Yun PENG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Chi KO of Nantou County (TW) for taiwan semiconductor manufacturing co., ltd., Keng-Chu LIN of Pingtung County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/28, H01L21/02, H01L21/762
CPC Code(s): H01L21/28158
Abstract: a device includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. the first conductor is in the first dielectric layer. the etch stop layer is over the first dielectric layer. the etch stop layer has a first surface facing the first dielectric layer and a second surface facing away from the first dielectric layer, and a concentration of carbon in the etch stop layer periodically varies from the first surface to the second surface. the second dielectric layer is over the etch stop layer. the second conductor is in the second dielectric layer and the etch stop layer and electrically connected to the first conductor.
Inventor(s): Cheng-Wei CHANG of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Kao-Feng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Min-Hsiu HUNG of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Hsiang CHAO of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Huang-Yi HUANG of Hsin-chu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ting LIN of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/285, H01L21/28, H01L29/417, H01L29/49, H01L29/66, H01L29/78
CPC Code(s): H01L21/28518
Abstract: the present disclosure relates to a method for fabricating a semiconductor structure. the method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a s/d region; depositing a titanium silicide layer over the s/d region with a first chemical vapor deposition (cvd) process. the first cvd process includes a first hydrogen gas flow. the method also includes depositing a titanium nitride layer over the insulating structure with a second cvd process. the second cvd process includes a second hydrogen gas flow. the first and second cvd processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.
Inventor(s): Li-Chao YIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yuling CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Lung YANG of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Hung-Bin LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/67
CPC Code(s): H01L21/67017
Abstract: a vacuum apparatus includes process chambers, and a transfer chamber coupled to the process chambers. the transfer chamber includes one or more vacuum ports, thorough which a gas inside the transfer chamber is exhausted, and vent ports, from which a vent gas is supplied. the one or more vacuum ports and the vent ports are arranged such that air flows from at least one of the vent ports to the one or more vacuum ports are line-symmetric with respect to a center line of the transfer chamber.
Inventor(s): Chien-Fa Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hsu-Shui Liu of Pingjhen City (TW) for taiwan semiconductor manufacturing co., ltd., Jiun-Rong Pai of Jhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Shou-Wen Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/67, H01L21/677, H01L21/68, H01L21/687
CPC Code(s): H01L21/67201
Abstract: the present disclosure relates to a method of programming an efem. the method includes placing an automatic teaching element within an efem chamber at a first time. the automatic teaching element is operated at a second time to measure one or more parameters corresponding to an initial position of an efem robot within the efem chamber. the automatic teaching element is removed from the efem chamber at a third time and then placed within the efem chamber at a fourth time. the automatic teaching element is operated at a fifth time to determine positional parameters describing a difference between the initial position and a new position of the efem robot. a second plurality of steps are determined based upon the positional parameters. the efem robot is configured to move along the second plurality of steps that extend along a path between first and second positions.
Inventor(s): Chi-Ming Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Eugene I-Chun Chen of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Shiung Tsai of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/762
CPC Code(s): H01L21/76254
Abstract: a method of forming a semiconductor-on-insulator (soi) substrate includes: forming a first dielectric layer on a first substrate; forming a buffer layer on a second substrate; forming a semiconductor cap on the buffer layer over the second substrate; forming a cleavage plane in the buffer layer; forming a second dielectric layer on the semiconductor cap after forming the cleavage plane; bonding the second dielectric layer on the second substrate to the first dielectric layer on the first substrate; performing a splitting process along the cleavage plane in the buffer layer; removing a first split buffer layer from the semiconductor cap; and removing a second split buffer layer from the second substrate.
Inventor(s): Hsin-Che Chiang of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Jeng-Ya David Yeh of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Sheng Liang of Changhua County (TW) for taiwan semiconductor manufacturing co., ltd., Ju-Li Huang of Nantou County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L21/311, H01L23/522, H01L23/532, H01L29/417
CPC Code(s): H01L21/7682
Abstract: in one exemplary aspect, a method for semiconductor manufacturing comprises forming first and second silicon nitride features on sidewall surfaces of a contact hole, where the contact hole is disposed in a dielectric layer and above a source/drain (s/d) feature. the method further comprises forming a contact plug in the contact hole, the contact plug being electrically coupled to the s/d feature, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride features via selective etching to form first and second air gaps, respectively.
Inventor(s): Pei-Wen WU of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chun-I TSAI of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Cheng HUNG of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Jyh-Cherng SHEU of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Sheng WANG of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Hsing TSAI of Chu-Pei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/768, H01L21/285, H01L29/45
CPC Code(s): H01L21/76846
Abstract: a metal adhesion layer may be formed on a bottom and a sidewall of a trench prior to formation of a metal plug in the trench. a plasma may be used to modify the phase composition of the metal adhesion layer to increase adhesion between the metal adhesion layer and the metal plug. in particular, the plasma may cause a shift or transformation of the phase composition of the metal adhesion layer to cause the metal adhesion layer to be composed of a (111) dominant phase. the (111) dominant phase of the metal adhesion layer increases adhesion between the metal adhesion layer.
Inventor(s): Yi-Jing Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jeng-Wei Yu of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Li-Wei Chou of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tsz-Mei Kwok of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/822, H01L21/8234, H01L21/8238, H01L21/84, H01L27/06, H01L27/088, H01L27/092, H01L29/417, H01L29/66, H01L29/78
CPC Code(s): H01L21/8221
Abstract: a semiconductor device includes a substrate, first and second fins over the substrate and extending upwardly in a first direction, an epitaxial material comprising a first portion, a second portion, and a third portion, and a conductive feature in contact with the epitaxial material. the first portion is located on the first fin, the second portion is located on the second fin, and the third portion is connected to the first and second portions. the third portion has a bottom surface bended upwardly with an apex located between the first and second fins. in a cross-sectional plane perpendicular to a lengthwise direction of the first and second fins, the bottom surface has a first straight line and a second straight line intersecting at the apex.
Inventor(s): Kuei-Ming Chang of New Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Rei-Jay Hsieh of Miaoli (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Han Wu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chie-luan Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L21/8238, H01L21/762, H01L21/8234, H01L27/092, H01L29/06, H01L29/08, H01L29/66, H01L29/78
CPC Code(s): H01L21/823878
Abstract: a device includes a first transistor, a second transistor, and a dielectric structure. the first transistor is over a substrate and has a first gate structure. the second transistor is over the substrate and has a second gate structure. the dielectric structure is between the first gate structure and the second gate structure. the dielectric structure has a width increasing from a bottom position of the dielectric structure to a first position higher than the bottom position of the dielectric structure. a width of the first gate structure is less than the width of the dielectric structure at the first position.
Inventor(s): Yu-Hsiang Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hsiu-Wen Hsueh of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Szu-Lin Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Sheh Huang of Hsin Chu City (TW) for taiwan semiconductor manufacturing co., ltd., Chloe Hsin-Yi Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Lin Lai of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/34, H01L23/522, H01L23/528
CPC Code(s): H01L23/34
Abstract: a semiconductor structure includes a substrate having a front side and a back side, one or more dielectric layers over the front side, and a conductive structure. the one or more dielectric layers include a thermal sensor region and two dummy regions sandwiching the thermal sensor region along a second direction from a top view. the thermal sensor region and the two dummy regions extend longitudinally along a first direction generally perpendicular to the second direction from the top view. the conductive structure is embedded in the thermal sensor region of the one or more dielectric layers. the conductive structure includes conductive lines parallel to each other and extending longitudinally along the first direction, and conductive bars and vias electrically connecting the conductive lines. the conductive lines in a same dielectric layer of the one or more dielectric layers are electrically connected one by one zigzaggedly from the top view.
Inventor(s): Shu-Shen Yeh of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chin-Hua Wang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Kuei Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Po-Yao Lin of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd., Shin-Puu Jeng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/367, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/498, H01L25/00, H01L25/065
CPC Code(s): H01L23/3675
Abstract: semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. in some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. as such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.
Inventor(s): Sheng-Tsung Hsiao of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Jen Yu Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Jung Wu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tung-Liang Shao of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hang Tung of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/473, H01L21/48, H01L21/56, H01L21/78, H01L23/00, H01L23/31, H01L23/498, H01L23/58
CPC Code(s): H01L23/473
Abstract: semiconductor devices including lids having liquid-cooled channels and methods of forming the same are disclosed. in an embodiment, a semiconductor device includes a first integrated circuit die; a lid coupled to the first integrated circuit die, the lid including a plurality of channels in a surface of the lid opposite the first integrated circuit die; a cooling cover coupled to the lid opposite the first integrated circuit die; and a heat transfer unit coupled to the cooling cover through a pipe fitting, the heat transfer unit being configured to supply a liquid coolant to the plurality of channels through the cooling cover.
Inventor(s): Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Chung Yee of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/48, H01L21/768, H01L23/00, H01L23/31
CPC Code(s): H01L23/481
Abstract: a semiconductor device includes a first die including a patterned conductive pad, a second die stacked over and electrically coupled to the first die, a bonding dielectric layer between the first and second dies, and a through die via penetrating through the first die and passing through the patterned conductive pad and the bonding dielectric layer. the second die includes a conductive pad directly over the patterned conductive pad. the bonding dielectric layer bonds the patterned conductive pad to the conductive pad, and the through die via directly lands on the conductive pad.
Inventor(s): Lin-Yu HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Li-Zhen YU of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Hao CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Chi CHUANG of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Lun CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/532
CPC Code(s): H01L23/5222
Abstract: a semiconductor device structure, along with methods of forming such, are described. the semiconductor device structure includes a device, a first dielectric material disposed over the device, and an opening is formed in the first dielectric material. the semiconductor device structure further includes a conductive structure disposed in the opening, and the conductive structure includes a first sidewall. the semiconductor device structure further includes a surrounding structure disposed in the opening, and the surrounding structure surrounds the first sidewall of the conductive structure. the surrounding structure includes a first spacer layer and a second spacer layer adjacent the first spacer layer. the first spacer layer is separated from the second spacer layer by an air gap.
Inventor(s): Anhao CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L21/8234, H01L23/532
CPC Code(s): H01L23/5223
Abstract: an integrated circuit includes a plurality of transistors and an interlevel dielectric layer formed over the transistors. the interlevel dielectric layer includes a first region and a second region with a higher dielectric constant than the first region. the difference in dielectric constant is produced by curing the first region shielding the second region from the curing. metal signal lines are formed in the first region. metal-on-metal capacitors are formed in the second region.
Inventor(s): Ting-Li Yang of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Hao Tsai of Zhongli City (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Da Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Han Chuang of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Hsueh-Sheng Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L21/48, H01L23/00, H01L23/528
CPC Code(s): H01L23/5226
Abstract: methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. in an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (ubm) structure over the first redistribution line, the first ubm structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second ubm structure over the second redistribution line, the second ubm structure extending through the second passivation layer, the second ubm structure being electrically isolated from the second redistribution line by the first passivation layer.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., An-Jhih Su of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Hsi Wu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Chih Chiou of Zhunan Township (TW) for taiwan semiconductor manufacturing co., ltd., Tsang-Jiuh Wu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Der-Chyang Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming Shih Yeh of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/522, H01L21/02, H01L21/033, H01L21/3105, H01L21/311, H01L21/321, H01L21/56, H01L21/683, H01L21/768, H01L23/00, H01L23/528, H01L23/538, H01L25/07, H01L25/075, H01L33/00, H01L33/06, H01L33/32, H01L33/38, H01L33/62
CPC Code(s): H01L23/5226
Abstract: a method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. in an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.
Inventor(s): Jhon Jhy LIAW of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/528, H01L21/285, H01L21/8238, H01L27/092, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L23/5286
Abstract: a method includes forming semiconductor sheets on a front-side of a semiconductive layer on a front-side of a substrate; forming a gate strip surrounding each of the semiconductor sheets; forming dielectric layers on the semiconductive layer and at opposite sides of the gate strip; forming source/drain structures on the dielectric layers and on either side of each of the semiconductor sheets; performing a planarization process on a back-side of the substrate to expose the semiconductive layer; etching the semiconductive layer from a back-side of the semiconductive layer to form a first opening exposing a first one of the dielectric layers, while remains covering a second one of the dielectric layers; selectively removing the first one of the dielectric layers through the first opening to from a second opening exposing one of the source/drain structures; forming a contact having back-side and front-side portions in the first and second openings.
Inventor(s): Kao-Cheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jui-Chien HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Pin-Dai SUE of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Huei CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/528, H01L21/8234, H01L27/088, H01L27/092
CPC Code(s): H01L23/5286
Abstract: semiconductor devices including a first upper channel structure, a first intermediate structure below the first upper channel structure, a first lower channel structure below the first intermediate structure, and a voltage source connected to the first lower channel structure, in which the first upper channel structure, the first intermediate structure, and the first lower channel structure comprise a first vertical assembly that provides an electrical connection between the voltage source and the first upper channel structure.
Inventor(s): Meng-Tsung KUO of Tainan City (TW) for taiwan semiconductor manufacturing co., ltd., Hui-Chang YU of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Kung HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Teng CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L23/10, H01L23/367, H01L25/065
CPC Code(s): H01L24/33
Abstract: a package structure is provided. the package structure includes a chip-containing structure over a substrate and a first adhesive element directly above the chip-containing structure. the first adhesive element has a first thermal conductivity. the package structure also includes multiple second adhesive elements directly above the chip-containing structure. the second adhesive elements are spaced apart from each other, each of the second adhesive elements has a second thermal conductivity, and the second thermal conductivity is greater than the first thermal conductivity. the package structure further includes a protective lid attached to the chip-containing structure through the first adhesive element and the second adhesive elements. the protective lid extends across opposite sidewalls of the chip-containing structure.
20240250061. WAFER BONDING METHOD_simplified_abstract_(taiwan semiconductor manufacturing co., ltd.)
Inventor(s): Yung-Chi Lin of Su-Lin City (TW) for taiwan semiconductor manufacturing co., ltd., Tsang-Jiuh Wu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Chih Chiou of Zhunan Township (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L23/00, B23K26/362, H01L21/3213, H01L25/00, H01L25/065
CPC Code(s): H01L24/80
Abstract: in an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Chung Yee of Taoyuan (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Ding Wang of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Chien-Hsun Lee of Chu-tung Town (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L21/48, H01L21/56, H01L21/768, H01L23/00, H01L23/31, H01L23/367, H01L23/498, H01L23/522, H01L23/538, H01L25/00, H01L25/18
CPC Code(s): H01L25/0652
Abstract: a semiconductor device and a method of making the same are provided. a first die and a second die are placed over a carrier substrate. a first molding material is formed adjacent to the first die and the second die. a first redistribution layer is formed overlying the first molding material. a through via is formed over the first redistribution layer. a package component is on the first redistribution layer next to the copper pillar. the package component includes a second redistribution layer. the package component is positioned so that it overlies both the first die and the second die in part. a second molding material is formed adjacent to the package component and the first copper pillar. a third redistribution layer is formed overlying the second molding material. the second redistribution layer is placed on a substrate and bonded to the substrate.
Inventor(s): Shu-Shen YEH of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Chen LAI of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Che-Chia YANG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Li-Ling LIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Yao LIN of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd., Shin-Puu JENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L25/065, H01L21/48, H01L21/56, H01L21/78, H01L23/31, H01L23/498
CPC Code(s): H01L25/0655
Abstract: a package structure is provided. the package structure includes a chip structure having opposite surfaces with different widths. the chip structure has an inclined sidewall between the opposite surfaces. the package structure also includes a protective layer laterally surrounding the chip structure.
Inventor(s): Cheng-Ming LIN of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Yen WOON of Taoyuan City (TW) for taiwan semiconductor manufacturing co., ltd., Szuya LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L27/0924
Abstract: dipole engineering techniques for devices of stacked device structures are disclosed herein. an exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives a p-dipole dopant from the p-dipole dopant source layer into the high-k dielectric layer, and forming at least one electrically conductive gate layer over the high-k dielectric layer after removing the p-dipole dopant source layer. a drive-in temperature of the thermal drive-in process is less than 600� c. (e.g., about 300� c. to about 500� c.). the p-dipole dopant can be titanium. the method can further include tuning thermal drive-in process parameters to provide the gate dielectric with a p-dipole dopant profile having a peak located at a high-k/interfacial interface �0.5 nm.
Inventor(s): Chi-Hsien Chung of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Tzu-Jui Wang of Fengshan City (TW) for taiwan semiconductor manufacturing co., ltd., Chia-Chi Hsiao of Tianzhong Township (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Hao Chuang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Jong Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14605
Abstract: an integrated chip including a first semiconductor substrate. the first semiconductor substrate includes a doped region. a first photodetector and a second photodetector are in the first semiconductor substrate. a trench isolation layer at least partially surrounds the first photodetector and the second photodetector and extends between the first photodetector and the second photodetector. the trench isolation layer has a first pair of sidewalls. the first semiconductor substrate extends from the first photodetector, between the first pair of sidewalls, to the second photodetector. the doped region is between the first pair of sidewalls. the first photodetector and a first gate partially form a first transistor. the second photodetector and a second gate partially form a second transistor. a second semiconductor substrate is over the first gate and the second gate. a third transistor is along the second semiconductor substrate. the third transistor is coupled to the first transistor.
Inventor(s): Harry-Hak-Lay Chuang of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Hsin Fu Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Hao Yeh of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/762, H01L21/768, H01L23/48, H01L29/78
CPC Code(s): H01L29/0607
Abstract: an integrated circuit (ic) device comprises a high voltage semiconductor device (hvsd) on a frontside of a semiconductor body and further comprises an electrode on a backside of the semiconductor body opposite the frontside. the hvsd may for example, be a transistor or some other suitable type of semiconductor device. the electrode has one or more gaps directly beneath the hvsd. the one or more gaps enhance the effectiveness of the electrode for improving the breakdown voltage of the hvsd.
Inventor(s): Hsiu-Yung LIN of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yen CHUANG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Min-Hao HONG of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/02, H01L29/78
CPC Code(s): H01L29/0649
Abstract: the present disclosure describes a semiconductor device with a fill structure. the semiconductor structure includes first and second fin structures on a substrate, an isolation region on the substrate and between the first and second fin structures, a first gate structure disposed on the first fin structure and the isolation region, a second gate structure disposed on the second fin structure and the isolation region, and the fill structure on the isolation region and between the first and second gate structures. the fill structure includes a dielectric structure between the first and second gate structures and an air gap enclosed by the dielectric structure. the air gap is below top surfaces of the first and second fin structures.
Inventor(s): Hung-Li CHIANG of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chao-Ching Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Tzu-Chiang Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., I-Sheng Chen of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/308, H01L21/8234, H01L27/088, H01L29/66, H01L29/78
CPC Code(s): H01L29/0649
Abstract: the structure of a semiconductor device with isolation structures between fet devices and a method of fabricating the semiconductor device are disclosed. a method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. the method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages
Inventor(s): Kuo-Cheng Chiang of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Huan-Chieh Su of Tianzhong Township (TW) for taiwan semiconductor manufacturing co., ltd., Shi Ning Ju of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Ting Pan of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/02, H01L21/3065, H01L21/308, H01L21/311, H01L21/762, H01L21/8234, H01L29/08, H01L29/10, H01L29/40, H01L29/423, H01L29/49, H01L29/66
CPC Code(s): H01L29/0673
Abstract: a method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.
Inventor(s): Shu-Wen SHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/417, H01L29/423, H01L29/66, H01L29/78, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a semiconductor device structure is provided. the device includes a plurality of semiconductor layers vertically stacked, and a gate electrode layer comprising an upper portion disposed between two adjacent gate spacers, the upper portion having a first diameter. the gate electrode layer also includes a lower portion disposed below the upper portion including a first part surrounding each semiconductor layer of the plurality of semiconductor layers and a second part adjacent the first part, the second part comprising a first section having a second diameter that is less than the first diameter, a second section below the first section, the second section having a third diameter different than the second diameter, and a third section below the second section, wherein the third section has a fourth diameter different than the second diameter and the third diameter, wherein the first and second parts are formed as an integral.
Inventor(s): Chih-Ching WANG of Kinmen (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Yang LEE of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Chang WEN of Kaohsiung (TW) for taiwan semiconductor manufacturing co., ltd., Jo-Tzu HUNG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Hsing HSIEH of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Lun CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/10, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L29/1033
Abstract: embodiments of the present disclosure provide a semiconductor device structure including a first channel layer formed of a first material, wherein the first channel layer has a first width, a second channel layer formed of a second material different from the first material, wherein the second channel layer has a second width less than the first width, and the second channel layer is in contact with a first surface of the first channel layer. the structure also includes a third channel layer formed of the second material, wherein the third channel layer has a third width less than the second width, and the third channel layer is in contact with a second surface of the first channel layer. the structure also includes a gate dielectric layer conformally disposed on the first channel layer, the second channel layer, and the third channel layer, and a gate electrode layer disposed on the gate dielectric layer.
Inventor(s): Wu-Wei TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi-Min CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yin-Hao WU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kai-Wen CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hai-Ching CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ming LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Te LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L29/40, H01L29/66, H01L29/786
CPC Code(s): H01L29/41733
Abstract: a semiconductor device and a manufacturing method thereof are provided. the semiconductor device includes a gate electrode, a gate insulating layer, an active layer, a dielectric layer, a source electrode, and a drain electrode. the gate insulating layer is disposed between the gate electrode and the active layer, the dielectric layer is disposed on a side of the active layer, and the source electrode and the drain electrode pass through the dielectric layer to electrically connect with the active layer, wherein a first contact surface is formed between the source electrode and the active layer, a second contact surface is formed between the drain electrode and the active layer, the first contact surface and the second contact surface are subjected to a plasma treatment or a deposition treatment to form a protective interface layer.
Inventor(s): Chun-Yuan Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing co., ltd., Huan-Chieh Su of Tianzhong Township (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Nan Yang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/417, H01L21/8234, H01L23/48, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/41733
Abstract: a method includes forming a gate electrode and a source/drain region over a bulk portion of a semiconductor substrate, forming a cut-metal-gate region to separate the gate electrode into a first portion and a second portion, forming a source/drain contact plug overlapping and electrically connected to the source/drain region, forming a first contact rail overlapping a portion of the cut-metal-gate region, removing the bulk portion of the semiconductor substrate, and etching the cut-metal-gate region to form a trench. a surface of the first contact rail is revealed to the trench. a via rail is formed in the trench, and the via rail is electrically connected to the source/drain region through the first contact rail.
Inventor(s): Chao-Hsun Wang of Taoyuan County (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Feng Yin of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Yi Chao of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Mei-Yun Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Yu Chang of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Chen-Yuan Kao of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/28, H01L29/45, H01L29/49, H01L29/66, H01L29/78
CPC Code(s): H01L29/42364
Abstract: a semiconductor structure includes a metal gate structure having a gate dielectric layer and a gate electrode. a topmost surface of the gate dielectric layer is above a topmost surface of the gate electrode. the semiconductor structure further includes a conductive layer disposed on the gate electrode of the metal gate structure, the conductive layer having a bottom portion disposed laterally between sidewalls of the gate dielectric layer and a top portion disposed above the topmost surface of the gate dielectric layer. the semiconductor structure further includes a contact feature in direct contact with the top portion of the conductive layer.
Inventor(s): Chih-Chao Chou of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Shi Ning Ju of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Wen-Ting Lan of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L29/08, H01L29/10, H01L29/66
CPC Code(s): H01L29/42392
Abstract: semiconductor device and the manufacturing method thereof are disclosed. an exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.
Inventor(s): Cheng-Ting Chung of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Bo Liao of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hou-Yu Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/423, H01L21/306, H01L21/311, H01L21/321, H01L29/06, H01L29/08, H01L29/10, H01L29/40, H01L29/66, H01L29/78
CPC Code(s): H01L29/42392
Abstract: semiconductor device and the manufacturing method thereof are disclosed herein. an exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.
Inventor(s): Te-Chih Hsiung of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Jyun-De Wu of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Chen Wang of Zhubei City (TW) for taiwan semiconductor manufacturing co., ltd., Yi-Chun Chang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yuan-Tien Tu of Puzih City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/45, H01L21/3105, H01L21/311, H01L23/522, H01L29/06, H01L29/40, H01L29/423
CPC Code(s): H01L29/456
Abstract: conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. in an embodiment, a semiconductor device includes a first interlayer dielectric (ild) layer over a transistor structure; a first contact extending through the first ild layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ild layer; a second ild layer over the first ild layer and the first contact; and a second contact extending through the second ild layer, the second contact being electrically coupled with the first contact.
Inventor(s): Kuo-Ju Chen of Taichung (TW) for taiwan semiconductor manufacturing co., ltd., Su-Hao Liu of Chiayi (TW) for taiwan semiconductor manufacturing co., ltd., Huicheng Chang of Tainan (TW) for taiwan semiconductor manufacturing co., ltd., Yee-Chia Yeo of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66
CPC Code(s): H01L29/6634
Abstract: disclosed is a method of fabricating a contact in a semiconductor device. the method includes: receiving a semiconductor structure having an opening into which the contact is to be formed; forming a metal layer in the opening; forming a bottom anti-reflective coating (barc) layer in the opening; performing implanting operations with a dopant on the barc layer and the metal layer, the performing implanting operations including controlling an implant energy level and controlling an implant dosage level to form a crust layer with a desired minimum depth on top of the barc layer; removing unwanted metal layer sections using wet etching operations, wherein the crust layer and barc layer protect remaining metal layer sections under the barc layer from metal loss during the wet etching operations; removing the crust layer and the barc layer; and forming the contact in the opening over the remaining metal layer sections.
Inventor(s): Sheng-Liang Pan of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chen Yung Tzu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Chieh Lee of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Chang Hsu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hung Chia-Yang of Kaohsiung City (TW) for taiwan semiconductor manufacturing co., ltd., Po-Chuan Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Guan-Xuan Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Huan-Just Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L29/08, H01L29/49, H01L29/78
CPC Code(s): H01L29/6656
Abstract: a method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. the method includes forming a second dielectric layer over the first dielectric layer. the method includes exposing a portion of the first dielectric layer. the method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.
Inventor(s): Chia-Hao Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Lin-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sheng-Tsung Wang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/768, H01L21/8234, H01L29/06, H01L29/417, H01L29/49, H01L29/78
CPC Code(s): H01L29/6656
Abstract: semiconductor devices and methods of forming the same are provided. a semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. a first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. the air gap is disposed below the upper portion of the dielectric feature.
Inventor(s): Xusheng Wu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chang-Miao Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Huiling SHANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/225, H01L21/265, H01L21/762, H01L29/06, H01L29/08, H01L29/423, H01L29/786
CPC Code(s): H01L29/66742
Abstract: a semiconductor structure includes a substrate, an oxide layer disposed over the substrate, a stack of semiconductor layers disposed over the oxide layer, and an epitaxial source/drain (s/d) feature disposed adjacent to the stack of semiconductor layers. a portion of the epitaxial s/d feature is horizontally surrounded by the oxide layer.
Inventor(s): Kun-Yi LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tai-Jung KUO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yunn-Shiuan LIU of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Zhen-Cheng WU of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chi On CHUI of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/768, H01L21/8234, H01L27/088, H01L29/40, H01L29/423, H01L29/78
CPC Code(s): H01L29/66795
Abstract: a semiconductor device structure, along with methods of forming such, are described. the structure includes a gate electrode disposed over a semiconductor substrate and a gate cut-fill structure disposed in the gate electrode to separate the gate electrode into two portions. the gate cut-fill structure includes a first liner, a second liner disposed on the first liner, and a dielectric material disposed on the second liner. the dielectric material has a “v” shaped cross-section.
Inventor(s): Chao-Hsuan Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Chia Tai of Zhubei (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Hsien Lin of Kaohsiung (TW) for taiwan semiconductor manufacturing co., ltd., Shun-Hui Yang of Jungli (TW) for taiwan semiconductor manufacturing co., ltd., Ryan Chia-Jen Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/28, H01L29/49, H01L29/78
CPC Code(s): H01L29/66795
Abstract: a method includes fabricating a semiconductor device, wherein the method includes depositing a coating layer on a first region and a second region under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. the method also includes applying processing gas to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region.
Inventor(s): I-Hsieh Wong of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Ting Chen of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Cheng Yang of Zhudong Township (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Ming Chen of Chu-Pei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/306, H01L21/3065, H01L21/311, H01L29/08, H01L29/78
CPC Code(s): H01L29/66818
Abstract: in an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.
Inventor(s): Ming-Heng TSAI of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Chun-Sheng LIANG of Changhua (TW) for taiwan semiconductor manufacturing co., ltd., Ta-Chun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/775, H01L29/06, H01L29/417, H01L29/423, H01L29/66
CPC Code(s): H01L29/775
Abstract: embodiments of the present disclosure provide a semiconductor device structure. in one embodiment, the semiconductor device structure includes a plurality of semiconductor layers vertically stacked over a substrate, a source/drain feature in contact with each of the plurality of the semiconductor layers, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, a source/drain contact disposed above the source/drain feature, a gate spacer disposed between the gate electrode layer and the source/drain contact, and an isolation structure extending through the gate electrode layer. the isolation structure includes a first portion having three sides covered by the gate electrode layer, the first portion having a top surface at a first elevation, and a second portion extended outwardly from the first portion, the second portion having a top surface at a second elevation that is lower than the first elevation.
Inventor(s): Lian-Jie LI of Shanghai City (CN) for taiwan semiconductor manufacturing co., ltd., Yan-Bin LU of Shanghai City (CN) for taiwan semiconductor manufacturing co., ltd., Feng HAN of Shanghai City (CN) for taiwan semiconductor manufacturing co., ltd., Shuai ZHANG of Shanghai City (CN) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/265, H01L21/266, H01L29/06, H01L29/10, H01L29/66
CPC Code(s): H01L29/7835
Abstract: a semiconductor device includes a gate structure, a drift region, a source region, a drain region, a first doped region, and a second doped region. the gate structure is over a semiconductor substrate. the drift region is in the semiconductor substrate and laterally extends past a first side of the gate structure. the source region is in the semiconductor substrate and adjacent a second side of the gate structure opposite the first side. the drain region is in the drift region. the first doped region is in the drift region and between the drain region and the gate structure. the second doped region is within the drift region. the second doped region forms a p-n junction with the first doped region at a bottom surface of the first doped region.
Inventor(s): Mauricio MANFRINI of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Han-Jong Chia of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/28, H01L29/66
CPC Code(s): H01L29/78391
Abstract: a semiconductor device includes a transistor and a ferroelectric tunnel junction. the ferroelectric tunnel junction is connected to a drain contact of the transistor. the ferroelectric tunnel junction includes a first electrode, a second electrode, a crystalline oxide layer, and a ferroelectric layer. the second electrode is disposed over the first electrode. the crystalline oxide layer and the ferroelectric layer are disposed in direct contact with each other in between the first electrode and the second electrode. the crystalline oxide layer comprises a crystalline oxide material. the ferroelectric layer comprises a ferroelectric material.
Inventor(s): Hsiao-Chun CHANG of Hukou Township (TW) for taiwan semiconductor manufacturing co., ltd., Guan-Jie SHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L21/324, H01L29/08, H01L29/10, H01L29/66
CPC Code(s): H01L29/785
Abstract: in a method of manufacturing a semiconductor device including a fin fet, a fin structure, which has an upper fin structure made of sige and a bottom fin structure made of a different material than the upper fin structure, is formed, a cover layer is formed over the fin structure, a thermal operation is performed on the fin structure covered by the cover layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper fin structure. the thermal operation changes a germanium distribution in the upper fin structure.
Inventor(s): Szu-Chi YANG of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Hsiang HUANG of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/78, H01L21/8234, H01L21/8238, H01L29/08, H01L29/165, H01L29/66
CPC Code(s): H01L29/7851
Abstract: a device includes a gate structure extending over a semiconductor channel region, and source/drain epitaxial structures at opposite sides of the gate structure. each of the source/drain epitaxial structures includes a bar-shaped epitaxial region and a cladding epitaxial layer cladding on the bar-shaped epitaxial region, the cladding epitaxial layer having a dopant concentration higher than a dopant concentration of the bar-shaped epitaxial region.
Inventor(s): Shahaji B. MORE of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Chun Hsiung TSAI of Xinpu Township (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/786, H01L21/02, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66
CPC Code(s): H01L29/78618
Abstract: in a method of manufacturing a semiconductor device, a fin structure is formed. the fin structure includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure, and a hard mask layer over the stacked layer. an isolation insulating layer is formed so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer. a sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. a first dielectric layer is formed, and a second dielectric layer made of a different material than the first dielectric layer is formed over the first dielectric layer. the second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer, thereby forming a wall fin structure.
Inventor(s): Liang-Yu Su of Yunlin County (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Wen Yao of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Hsiao-Chin Tuan of Ju Dong County (TW) for taiwan semiconductor manufacturing co., ltd., Ming-Ta Lei of Hsin-Chu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L29/93, H01L27/08, H01L29/06, H01L29/66
CPC Code(s): H01L29/93
Abstract: various embodiments of the present disclosure are directed towards an integrated chip including a first doped region in a substrate and comprising a first doping type. a gate structure is over the first doped region. a pair of contact regions are in the substrate on opposing sides of the gate structure and comprising the first doping type. the first doped region continuously laterally extends between the pair of contact regions and contacts the pair of contact regions. a second doped region is in the substrate and along a bottom of the first doped region. the second doped region comprises a second doping type opposite the first doping type.
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing co., ltd., Hsien-Wei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Jie Chen of New Taipei City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H01L33/52, G02B6/12, G02B6/42, H01L25/16, H01L31/0203, H01L31/0232, H01L31/18, H01L33/58, H01L33/62
CPC Code(s): H01L33/52
Abstract: a manufacturing method of a semiconductor package includes the following steps. a photonic die is provided, wherein the photonic die includes an optical coupler. an electronic die is bonded over the photonic die. an encapsulating material is provided over the photonic die, wherein the encapsulating material at least laterally encapsulates the electronic die. a substrate is bonded over the encapsulated electronic die. a lens structure is formed over the photonic die, wherein the lens structure is overlapped with the optical coupler from a top view.
Inventor(s): Cheng-Yu LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yung-Chen CHIEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jia-Hong GAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Jerry Chang Jui KAO of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hui-Zhong ZHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H03K3/3562, H03K3/012, H03K3/037, H03K3/356
CPC Code(s): H03K3/35625
Abstract: an integrated circuit (ic) device includes a master latch circuit having a data output, a slave latch circuit having a data input electrically coupled to the data output of the master latch circuit, and a clock circuit electrically coupled to the master latch circuit and the slave latch circuit. the slave latch circuit is physically between the master latch circuit and at least a part of the clock circuit.
Inventor(s): Feng-Ching Chu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing co., ltd., Feng-Cheng Yang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Ming Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B10/00, H01L21/02, H01L21/306, H01L21/3105, H01L29/06, H01L29/08, H01L29/10, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H10B10/12
Abstract: a semiconductor device according to the present disclosure includes a gate-all-around (gaa) transistor in a first device area and a fin-type field effect transistor (finfet) in a second device area. the gaa transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. the finfet includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. the fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.
Inventor(s): Kao-Cheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Hidehiro FUJIWARA of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yen Lin CHUNG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei Min CHAN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Huei CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/125
Abstract: an integrated circuit (ic) device includes a memory array including a plurality of memory cells, a first word line over the memory array and electrically coupled to at least one first memory cell among the plurality of memory cells, and a second word line under the memory array and electrically coupled to at least one second memory cell among the plurality of memory cells. each memory cell among the plurality of memory cells includes complementary field-effect transistor (cfet) devices.
Inventor(s): Yen Lin CHUNG of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Kao-Cheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Wei Min CHAN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Huei CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B10/00, G06F30/392, G11C11/419
CPC Code(s): H10B10/18
Abstract: a memory macro includes an input/output (i/o) circuit positioned in a semiconductor wafer, a column of memory cells including first and second subsets of contiguous memory cells extending away from the i/o circuit in the semiconductor wafer, wherein the first subset is positioned between the i/o circuit and the second subset, a first bit line coupled to the i/o circuit and extending on one of a frontside or a backside of the semiconductor wafer along the first subset and terminating at the second subset, and a second bit line coupled to the i/o circuit and extending on the other of the frontside or the backside along the first and second subsets. each memory cell of the first subset is electrically connected to the first bit line, and each memory cell of the second subset is electrically connected to the second bit line.
Inventor(s): Sheng-Chen Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Sai-Hooi Yeong of Hsinchu County (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd., Han-Jong Chia of Hsinchu City (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B51/20, H01L29/417, H10B51/00, H10B51/10, H10B51/30
CPC Code(s): H10B51/20
Abstract: a memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and conductive pillars. the first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. the first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure. the gate dielectric layers are respectively located in one of the cell regions, and cover opposing sidewalls of the first stacking structure and the second stacking structure as well as opposing sidewalls of the first isolation structures. the channel layers respectively cover an inner surface of one of the gate dielectric layers. the conductive pillars stand on the substrate within the cell regions, and are laterally surrounded by the channel layers, where at least two of the conductive pillars are located in each of the cell regions, and the at least two conductive pillars in each of the cell regions are laterally separated from one another.
Inventor(s): Chung-Te Lin of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Yen-Chung Ho of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Pin-Cheng Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Han-Ting Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Katherine Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B61/00, G06F3/06, G11C11/16, H10N50/01, H10N50/80
CPC Code(s): H10B61/20
Abstract: an embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (mram) circuitry integrated into the chip. the mram circuitry includes a plurality of mram cells. the mram cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. the cache memory includes multiple cache levels.
Inventor(s): Tai-Yen Peng of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Tsung-Hsien Chang of Shalu Township (TW) for taiwan semiconductor manufacturing co., ltd., Yu-Shu Chen of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chih-Yuan Ting of Taipei (TW) for taiwan semiconductor manufacturing co., ltd., Jyu-Horng Shieh of Hsinchu (TW) for taiwan semiconductor manufacturing co., ltd., Chung-Te Lin of Tainan (TW) for taiwan semiconductor manufacturing co., ltd.
IPC Code(s): H10B61/00, G11C11/16, H10N50/01, H10N50/10
CPC Code(s): H10B61/22
Abstract: a semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (mtjs), where the first mtjs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second mtjs, where the second mtjs are in the first dielectric layer.
Taiwan Semiconductor Manufacturing Co., Ltd. patent applications on July 25th, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- B08B9/04
- C23C16/44
- H01L21/67
- CPC B08B9/04
- Taiwan semiconductor manufacturing co., ltd.
- F16F7/10
- CPC F16F7/10
- G02B6/12
- G02B6/136
- CPC G02B6/12004
- G03F1/22
- G03F1/52
- G03F1/80
- G03F7/20
- CPC G03F1/22
- G03F7/00
- CPC G03F7/70033
- G11C11/16
- CPC G11C11/1697
- G11C16/28
- G11C16/10
- H03K19/20
- CPC G11C16/28
- G11C17/16
- G11C17/18
- H10B20/20
- CPC G11C17/16
- H01J37/08
- H01J37/317
- CPC H01J37/08
- H01L21/02
- CPC H01L21/02603
- H01L21/027
- G03F7/16
- H01L21/033
- H01L21/311
- H01L21/3213
- H01L21/768
- H01L21/8238
- CPC H01L21/0276
- CPC H01L21/0331
- H01L21/225
- H01L21/22
- H01L27/092
- H01L29/423
- H01L29/66
- H01L29/78
- H01L29/786
- CPC H01L21/225
- H01L21/265
- H01L21/266
- H01L21/28
- H10B10/00
- CPC H01L21/26513
- H01L21/762
- CPC H01L21/28158
- H01L21/285
- H01L29/417
- H01L29/49
- CPC H01L21/28518
- CPC H01L21/67017
- H01L21/677
- H01L21/68
- H01L21/687
- CPC H01L21/67201
- CPC H01L21/76254
- H01L23/522
- H01L23/532
- CPC H01L21/7682
- H01L29/45
- CPC H01L21/76846
- H01L21/822
- H01L21/8234
- H01L21/84
- H01L27/06
- H01L27/088
- CPC H01L21/8221
- H01L29/06
- H01L29/08
- CPC H01L21/823878
- H01L23/34
- H01L23/528
- CPC H01L23/34
- H01L23/367
- H01L21/48
- H01L21/56
- H01L23/00
- H01L23/31
- H01L23/498
- H01L25/00
- H01L25/065
- CPC H01L23/3675
- H01L23/473
- H01L21/78
- H01L23/58
- CPC H01L23/473
- H01L23/48
- CPC H01L23/481
- CPC H01L23/5222
- CPC H01L23/5223
- CPC H01L23/5226
- H01L21/3105
- H01L21/321
- H01L21/683
- H01L23/538
- H01L25/07
- H01L25/075
- H01L33/00
- H01L33/06
- H01L33/32
- H01L33/38
- H01L33/62
- H01L29/775
- CPC H01L23/5286
- H01L23/10
- CPC H01L24/33
- B23K26/362
- CPC H01L24/80
- H01L25/18
- CPC H01L25/0652
- CPC H01L25/0655
- CPC H01L27/0924
- H01L27/146
- CPC H01L27/14605
- CPC H01L29/0607
- CPC H01L29/0649
- H01L21/308
- H01L21/3065
- H01L29/10
- H01L29/40
- CPC H01L29/0673
- CPC H01L29/1033
- CPC H01L29/41733
- CPC H01L29/42364
- CPC H01L29/42392
- H01L21/306
- CPC H01L29/456
- CPC H01L29/6634
- CPC H01L29/6656
- CPC H01L29/66742
- CPC H01L29/66795
- CPC H01L29/66818
- CPC H01L29/775
- CPC H01L29/7835
- CPC H01L29/78391
- H01L21/324
- CPC H01L29/785
- H01L29/165
- CPC H01L29/7851
- CPC H01L29/78618
- H01L29/93
- H01L27/08
- CPC H01L29/93
- H01L33/52
- G02B6/42
- H01L25/16
- H01L31/0203
- H01L31/0232
- H01L31/18
- H01L33/58
- CPC H01L33/52
- H03K3/3562
- H03K3/012
- H03K3/037
- H03K3/356
- CPC H03K3/35625
- CPC H10B10/12
- CPC H10B10/125
- G06F30/392
- G11C11/419
- CPC H10B10/18
- H10B51/20
- H10B51/00
- H10B51/10
- H10B51/30
- CPC H10B51/20
- H10B61/00
- G06F3/06
- H10N50/01
- H10N50/80
- CPC H10B61/20
- H10N50/10
- CPC H10B61/22
