TEXAS INSTRUMENTS INCORPORATED patent applications on March 13th, 2025
Patent Applications by TEXAS INSTRUMENTS INCORPORATED on March 13th, 2025
TEXAS INSTRUMENTS INCORPORATED: 18 patent applications
TEXAS INSTRUMENTS INCORPORATED has applied for patents in the areas of G01R31/3185 (3), H01L21/56 (2), H01L23/00 (2), H01L23/31 (2), G05F1/46 (2) B01L3/502715 (1), H01L23/5256 (1), H04L69/22 (1), H04B3/54 (1), H03B5/364 (1)
With keywords such as: terminal, circuit, input, coupled, transistor, output, device, data, control, and current in patent application abstracts.
Patent Applications by TEXAS INSTRUMENTS INCORPORATED
Inventor(s): Sebastian MEIER of Muenchen (DE) for texas instruments incorporated, Ernst MUELLNER of Muenchen (DE) for texas instruments incorporated
IPC Code(s): B01L3/00, G01N27/22
CPC Code(s): B01L3/502715
Abstract: example packaged integrated circuit (ic) sensors comprise a semiconductor substrate; a back end of line (beol) structure on the semiconductor substrate, the beol structure including multiple microfluidic channels, each microfluidic channel including a flow control device configured to selectively permit and restrict flow of fluids; multiple fluid sensors including first and second fluid sensors in the beol structure; a main reaction reservoir on the beol structure configured to store a reagent, in which the reagent is operable to replicate a nucleic strand in a biological sample to cause a ph change, and the first fluid sensor is exposed in the main reaction reservoir; an auxiliary reservoir on the beol structure and coupled to the main reaction reservoir via a microfluid channel of the multiple microfluidic channels, in which the second fluid sensor is exposed in the auxiliary reaction reservoir; and a controller coupled to the first and second fluid sensors.
Inventor(s): Lee D. Whetsel of Parker TX (US) for texas instruments incorporated
IPC Code(s): G01R31/3177, G01R31/3185, G06F9/30, G06F11/34, G06F11/36
CPC Code(s): G01R31/3177
Abstract: the disclosure describes a novel method and apparatus for improving the operation of a tap architecture in a device through the use of command signal inputs to the tap architecture. in response to a command signal input, the tap architecture can perform streamlined and uninterrupted update, capture and shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. the command signals can be input to the tap architecture via the devices dedicated tms or tdi inputs or via a separate cmd input to the device.
20250085346. MERGED PARAMETRIC SCAN TOPOLOGY_simplified_abstract_(texas instruments incorporated)
Inventor(s): Abhishek Chaudhary of Nagpur (IN) for texas instruments incorporated, Grant Ford of Flower Mound TX (US) for texas instruments incorporated, Rubin A. Parekhji of Bangalore (IN) for texas instruments incorporated, Edward C. Suder of Garland TX (US) for texas instruments incorporated
IPC Code(s): G01R31/3185
CPC Code(s): G01R31/318572
Abstract: methods and apparatus for boundary scan. in one example, a circuit includes at least one first input/output (i/o) device, at least one boundary scan element coupled to the at least one first i/o device, and at least one second i/o device coupled to the at least one boundary scan element. the circuit may further include a test controller coupled to the at least one boundary scan element and configured to control the at least one boundary scan element to drive the at least one first i/o device and the at least one second i/o device with a binary test signal.
Inventor(s): Rinu MATHEW of Kerala (IN) for texas instruments incorporated, Vineet KHURANA of New Delhi (IN) for texas instruments incorporated, Anand Kumar G of Bengaluru (IN) for texas instruments incorporated, Aniruddha PERIYAPATNA NAGENDRA of Bangalore (IN) for texas instruments incorporated, Venkatesh KADLIMATTI of Karnataka (IN) for texas instruments incorporated, Torjus Lyng KALLERUD of Oslo (NO) for texas instruments incorporated
IPC Code(s): G05F1/46, G01R17/04, H02M1/00, H02M3/156, H02M3/157
CPC Code(s): G05F1/462
Abstract: in an example, a device includes a controller and a direct current (dc)-to-dc converter coupled to the controller and configured to provide a load current to a load. the device also includes a low-dropout (ldo) regulator coupled to the dc-to-dc converter. the controller includes digital logic, and the digital logic is configured to determine the load current. the digital logic is configured to turn on the ldo regulator if the load current is above a predetermined threshold. the digital logic is also configured to turn off the ldo regulator if the load current is below the predetermined threshold.
Inventor(s): Chizim Okpara of Tucson AZ (US) for texas instruments incorporated
IPC Code(s): G05F1/575, G05F1/46, G05F3/26
CPC Code(s): G05F1/575
Abstract: an example apparatus includes: voltage source circuitry having a terminal; a first transistor having a first terminal and a control terminal, the control terminal of the first transistor coupled to the terminal of the voltage source circuitry; current mirror circuitry having a first terminal and a second terminal, the first terminal of the current mirror circuitry coupled to the first terminal of the first transistor; and a second transistor having a control terminal coupled to the second terminal of the current mirror circuitry.
20250086107. ADDRESS SPACE MAPPING_simplified_abstract_(texas instruments incorporated)
Inventor(s): Yaron Alpert of Hod Hasharon (IL) for texas instruments incorporated, Barak Cherches of Ramat-Hakovesh (IL) for texas instruments incorporated, Guy Shubeli of Ramat-Hasharon (IL) for texas instruments incorporated, Yoav Ben-Yehezkel of Netanya (IL) for texas instruments incorporated
IPC Code(s): G06F12/02, G06F12/14
CPC Code(s): G06F12/0292
Abstract: in an embodiment, a method includes receiving a logical address from a primary device and determining an address header based on the logical address. the method also includes determining an offset value based on the address header and applying the offset value to a first portion of the logical address to create an offset address portion. the method further includes generating a physical address that includes the address header and the offset address portion and accessing a physical resource using the physical address.
Inventor(s): Geet Govind Modi of Cupertino CA (US) for texas instruments incorporated, Sumantra Seth of Bangalore (IN) for texas instruments incorporated, Subhashish Mukherjee of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G06F13/20, G06F1/08
CPC Code(s): G06F13/20
Abstract: a system for data transmission includes a physical (phy) layer which has a rate detection module which determines an adopted clock rate. the rate detection module provides a rate detection signal indicative of the adopted clock rate. the phy layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. the phy layer includes a phy interface which has a first input coupled to receive the reference clock output, a data input and a data output. the phy interface receives data from a mac interface at the data input and transmits data to the mac interface through the data output responsive to the reference clock output.
Inventor(s): Naveen Ambalametil Narayanan of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G06Q50/18, H04L9/32
CPC Code(s): G06Q50/184
Abstract: devices, instructions stored on non-transitory processor-readable mediums, and programming tools are provided. in an example, instructions specify reading a first customer identification value from a first memory on a device; reading a second customer identification value from a first field in a certificate; determining whether the first customer identification value matches the second customer identification value; permitting application data to be read from a second field in the certificate in response to determining that the first customer identification value matches the second customer identification value; and permitting the application data to be written to a second memory on the device in response to determining that the first customer identification value matches the second customer identification value.
20250087539. SCAN TESTABLE THROUGH SILICON VIAS_simplified_abstract_(texas instruments incorporated)
Inventor(s): Lee D. Whetsel of Parker TX (US) for texas instruments incorporated
IPC Code(s): H01L21/66, G01R31/28, G01R31/3185, H01L23/48, H01L25/065
CPC Code(s): H01L22/34
Abstract: the disclosure describes a novel method and apparatus for testing different types of tsvs in a single die or different types of tsv connections in a stack of die. the testing is facilitated by test circuitry associated with each type of tsv. the test circuitry includes a scan cell adapted for testing tsvs.
Inventor(s): Nazila Dadvand of Redmond WA (US) for texas instruments incorporated, Bernardo Gallegos of McKinney TX (US) for texas instruments incorporated
IPC Code(s): H01L23/495, H01L21/48, H01L21/56, H01L23/00, H01L23/31
CPC Code(s): H01L23/49582
Abstract: a semiconductor package includes a pad and leads, the pad and leads including a base metal predominantly including copper, a first plated metal layer predominantly including nickel in contact with the base metal, and a second plated metal layer predominantly including silver in contact with the first plated metal layer. the first plated metal layer has a first plated metal layer thickness of 0.1 to 5 microns, and the second plated metal layer has a second plated metal layer thickness of 0.2 to 5 microns. the semiconductor package further includes an adhesion promotion coating predominantly including silver oxide in contact with the second plated metal layer opposite the first plated metal layer, a semiconductor die mounted on the pad, a wire bond extending between the semiconductor die and a lead of the leads, and a mold compound covering the semiconductor die and the wire bond.
20250087583. FAIL-OPEN ISOLATOR_simplified_abstract_(texas instruments incorporated)
Inventor(s): Ujwal RADHAKRISHNA of San Jose CA (US) for texas instruments incorporated, Vinod RAI of San Jose CA (US) for texas instruments incorporated, Yogesh RAMADASS of San Jose CA (US) for texas instruments incorporated, Anant KAMATH of Bengaluru (IN) for texas instruments incorporated, Kashyap BAROT of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): H01L23/525, H02H3/04
CPC Code(s): H01L23/5256
Abstract: a device includes first and second device terminals, a fuse, a first circuit, a first transistor, and a control circuit. the fuse terminal couples to the first device terminal. the first circuit couples to the second fuse terminal. the second fuse terminal has a first voltage. the first transistor has a first control input and first and second current terminals. the first current terminal couples to the second fuse terminal, and the second current terminal couples to the second device terminal. the control circuit: turns “on” the first transistor into a saturation region if the first voltage exceeds a threshold and a current through the fuse exceeds a trip threshold current of the fuse; and turns “on” the first transistor into a linear region if the first voltage exceeds a threshold and a current through the fuse is below the trip threshold current of the fuse.
Inventor(s): Woochan Kim of Sunnyvale CA (US) for texas instruments incorporated, Masamitsu Matasuura of Beppu (JP) for texas instruments incorporated, Mutsumi Masumoto of Beppu (JP) for texas instruments incorporated, Kengo Aoya of Beppu (JP) for texas instruments incorporated, Hau Thanh Nguyen of San Jose CA (US) for texas instruments incorporated, Vivek Kishorechand Arora of San Jose CA (US) for texas instruments incorporated, Anindya Poddar of Sunnyvale CA (US) for texas instruments incorporated, Hideaki Matsunaga of Beppu (JP) for texas instruments incorporated
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L23/00, H01L23/31
CPC Code(s): H01L23/5389
Abstract: in one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. the package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. the package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.
Inventor(s): Robert Allan Neidorff of Bedford NH (US) for texas instruments incorporated
IPC Code(s): H02M1/08, H03K3/012
CPC Code(s): H02M1/08
Abstract: a dynamic scaling circuit includes: a damping control circuit; a sampling circuit; and a controller. the damping control circuit has a first input, a second input, a third input, an output, and a ground terminal. the sampling circuit has a first input, a second input, an output, and a ground terminal. the first input of the sampling circuit is coupled to the output of the damping control circuit. the controller has an input, a first output, a second output, and a third output. the first output of the controller is coupled to the second input of the damping control circuit. the second output of the controller is coupled to the third input of the damping control circuit. the third output of the controller is coupled to the second input of the sampling circuit.
Inventor(s): Avadhut JUNNARKAR of McKinney TX (US) for texas instruments incorporated, Mustapha El-Markhi of Richardson TX (US) for texas instruments incorporated, Vikram MANI of Plano TX (US) for texas instruments incorporated
IPC Code(s): H02M1/34, H02M1/00, H02M3/158
CPC Code(s): H02M1/342
Abstract: a circuit includes: an output terminal; a first transistor; and a clamp circuit. the first transistor has a first terminal, a second terminal, and a control terminal. the second terminal of the first transistor coupled to the output terminal. the clamp circuit has a second transistor and a clamp controller. the second transistor has a first terminal, a second terminal, and a control terminal. the clamp controller has a first terminal, a second terminal, and a third terminal. the first terminal of the second transistor is coupled to the control terminal of the first transistor. the third terminal of the clamp controller is coupled to the control terminal of the second transistor. the clamp controller includes a capacitor having a first terminal and a second terminal. the first terminal of the capacitor is coupled to the third terminal of the clamp controller.
20250088148. BAW RESONATOR BASED OSCILLATOR_simplified_abstract_(texas instruments incorporated)
Inventor(s): Ajay Kumar REDDY of Srikakulam (IN) for texas instruments incorporated, Arpan THAKKAR of Bangalore (IN) for texas instruments incorporated, Peeyoosh MIRAJKAR of Bangalore (IN) for texas instruments incorporated, Bichoy BAHR of Allen TX (US) for texas instruments incorporated
IPC Code(s): H03B5/36, H03K5/00
CPC Code(s): H03B5/364
Abstract: a circuit includes a resonator, a transistor pair, and a common-mode feedback circuit. the transistor pair is cross-coupled across the resonator. the common-mode feedback circuit is coupled to the transistor pair. the common-mode feedback circuit includes first and second degeneration cells. the second degeneration cell is connected in parallel with the first degeneration cell. the second degeneration cell is configured to switchably vary a current flow through the transistor pair.
20250088214. DATA TRANSMISSION VIA POWER LINE_simplified_abstract_(texas instruments incorporated)
Inventor(s): Suzanne Mary Vining of Plano TX (US) for texas instruments incorporated, Gary Chard of Murphy TX (US) for texas instruments incorporated, Win Naing Maung of Plano TX (US) for texas instruments incorporated, Mark Alan McAdams of Plano TX (US) for texas instruments incorporated
IPC Code(s): H04B3/54, G06F13/42
CPC Code(s): H04B3/54
Abstract: at least some aspects of the present disclosure provide for a method. in some examples, the method includes receiving 2-line data in an embedded universal serial bus (eusb) format. the method further includes encoding the 2-line data into a single signal. the single signal comprises a first symbol corresponding to a first state change of the 2-line data and a second symbol corresponding to a second state change of the 2-line data.
Inventor(s): Anand G. Dabak of Plano TX (US) for texas instruments incorporated, Badri N Varadarajan of Mountain View CA (US) for texas instruments incorporated, Il Han Kim of Allen TX (US) for texas instruments incorporated, Tarkesh Pande of Richardson TX (US) for texas instruments incorporated
IPC Code(s): H04L69/22, H04B1/69, H04B3/30, H04B3/54, H04B10/11
CPC Code(s): H04L69/22
Abstract: methods for building, transmitting, and receiving frame structures in power line communications (plc) are described. various techniques described herein provide a preamble design using one or more symbols. one or more preamble symbols may be interspersed within a header portion of a plc frame to facilitate estimation of a frame boundary and/or sampling frequency offset, for example, in the presence of impulsive noise.
Inventor(s): Niraj NANDAN of Plano TX (US) for texas instruments incorporated, Mihit Narendra MODY of Bangalore (IN) for texas instruments incorporated, Rajasekhar ALLU of Plano TX (US) for texas instruments incorporated
IPC Code(s): H04N25/77
CPC Code(s): H04N25/77
Abstract: in an example, a method includes receiving image data of an input image having lines therein. the method also includes storing a first portion of the image data in a circular buffer in a first memory, wherein the first portion begins at a circular buffer start line in the input image and ends at a circular buffer end line in the input image. the method includes storing a second portion of the image data in a linear buffer in a second memory, where the second portion is non-overlapping with the first portion. the method includes processing the second portion of the image data to produce a first block of an output image. the method includes processing the first portion of the image data to produce a second block of the output image.
TEXAS INSTRUMENTS INCORPORATED patent applications on March 13th, 2025
- TEXAS INSTRUMENTS INCORPORATED
- B01L3/00
- G01N27/22
- CPC B01L3/502715
- Texas instruments incorporated
- G01R31/3177
- G01R31/3185
- G06F9/30
- G06F11/34
- G06F11/36
- CPC G01R31/3177
- CPC G01R31/318572
- G05F1/46
- G01R17/04
- H02M1/00
- H02M3/156
- H02M3/157
- CPC G05F1/462
- G05F1/575
- G05F3/26
- CPC G05F1/575
- G06F12/02
- G06F12/14
- CPC G06F12/0292
- G06F13/20
- G06F1/08
- CPC G06F13/20
- G06Q50/18
- H04L9/32
- CPC G06Q50/184
- H01L21/66
- G01R31/28
- H01L23/48
- H01L25/065
- CPC H01L22/34
- H01L23/495
- H01L21/48
- H01L21/56
- H01L23/00
- H01L23/31
- CPC H01L23/49582
- H01L23/525
- H02H3/04
- CPC H01L23/5256
- H01L23/538
- CPC H01L23/5389
- H02M1/08
- H03K3/012
- CPC H02M1/08
- H02M1/34
- H02M3/158
- CPC H02M1/342
- H03B5/36
- H03K5/00
- CPC H03B5/364
- H04B3/54
- G06F13/42
- CPC H04B3/54
- H04L69/22
- H04B1/69
- H04B3/30
- H04B10/11
- CPC H04L69/22
- H04N25/77
- CPC H04N25/77
