TEXAS INSTRUMENTS INCORPORATED patent applications on January 23rd, 2025
Patent Applications by TEXAS INSTRUMENTS INCORPORATED on January 23rd, 2025
TEXAS INSTRUMENTS INCORPORATED: 26 patent applications
TEXAS INSTRUMENTS INCORPORATED has applied for patents in the areas of G06F12/0891 (4), G06F12/0855 (3), G06F13/16 (3), G06F9/30 (3), G11C7/10 (3) G06F12/128 (2), G01R31/318552 (1), H03G3/34 (1), H04N23/88 (1), H04N23/843 (1)
With keywords such as: circuit, input, output, coupled, terminal, data, voltage, configured, transistor, and control in patent application abstracts.
Patent Applications by TEXAS INSTRUMENTS INCORPORATED
Inventor(s): Arnab Khawas of Bangalore (IN) for texas instruments incorporated, Gokul Sabada of Bangalore (IN) for texas instruments incorporated, Madhavan Sainath Rao Pissay of Hyderabad (IN) for texas instruments incorporated, Badarish Subbannavar of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G01R31/3185, G01R31/317
CPC Code(s): G01R31/318552
Abstract: embodiments disclosed herein relate to clock gating. an example integrated circuit includes an oscillator that outputs a clock signal to a clock gating system that generates and provides a gated clock signal to a data storage circuit. the clock gating system includes a first digital logic circuit having an input coupled to the oscillator to receive the clock signal, an active-low latch that includes an input coupled to an output of the first digital logic circuit and an input coupled to receive an enable signal, a second digital logic circuit that includes an input coupled to the oscillator and an input coupled to the output of the active-low latch, and an active-high latch that includes an input coupled to the output of the second digital logic circuit, an input coupled to receive the enable signal, and an output configured to provide a gated clock signal to the data storage circuit.
20250028343. IN SITU STRAIN COMPENSATION AFE_simplified_abstract_(texas instruments incorporated)
Inventor(s): Divya Kaur of Bangalore (IN) for texas instruments incorporated, Vinod Menezes of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G05F1/565
CPC Code(s): G05F1/565
Abstract: a circuit () includes a voltage reference circuit () that includes an output terminal (), wherein the voltage reference circuit () is configured to generate an output voltage at the output terminal () having a first transfer function of voltage with respect to strain. the circuit () also includes a strain compensation circuit () having an input terminal connected to the output terminal () of the voltage reference circuit, and having a strain compensation circuit output terminal (). the strain compensation circuit () is configured to receive the output voltage comprising the first transfer function at the input terminal. the strain compensation circuit () has a second transfer function of voltage with respect to strain that is substantially opposite that of the first transfer function, thereby outputting a compensated voltage at the strain compensation circuit output terminal () that is substantially independent of strain.
Inventor(s): Devanathan Varadarajan of Allen TX (US) for texas instruments incorporated
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0653
Abstract: an example device includes: converter circuitry having an output configured to couple to a first memory circuit from a plurality of memory circuits, the converter circuitry configured to: receive a first instruction formatted with a uniform protocol; and convert the first instruction from the uniform protocol to a protocol specific to the first memory circuit; logic circuitry having an input configured to couple to the first memory circuit, the logic circuitry configured to: receive a first result of the first instruction from the first memory circuit; and responsive to a second instruction, combine the first result with other results from ones of the plurality of memory circuits into an output.
20250028551. GLOBAL COHERENCE OPERATIONS_simplified_abstract_(texas instruments incorporated)
Inventor(s): Abhijeet Ashok CHACHAD of Plano TX (US) for texas instruments incorporated, Naveen BHORIA of Plano TX (US) for texas instruments incorporated, David Matthew THOMPSON of Dallas TX (US) for texas instruments incorporated, Neelima MURALIDHARAN of Murphy TX (US) for texas instruments incorporated
IPC Code(s): G06F9/46, G06F9/30, G06F9/38, G06F9/448, G06F9/48, G06F9/54, G06F11/30, G06F12/0804, G06F12/0811, G06F12/0813, G06F12/0817, G06F12/0831, G06F12/0855, G06F12/0871, G06F12/0888, G06F12/0891, G06F12/12, G06F12/121, G06F13/16
CPC Code(s): G06F9/467
Abstract: a method includes receiving, by a l2 controller, a request to perform a global operation on a l2 cache and preventing new blocking transactions from entering a pipeline coupled to the l2 cache while permitting new non-blocking transactions to enter the pipeline. blocking transactions include read transactions and non-victim write transactions. non-blocking transactions include response transactions, snoop transactions, and victim transactions. the method further includes, in response to an indication that the pipeline does not contain any pending blocking transactions, preventing new snoop transactions from entering the pipeline while permitting new response transactions and victim transactions to enter the pipeline; in response to an indication that the pipeline does not contain any pending snoop transactions, preventing, all new transactions from entering the pipeline; and, in response to an indication that the pipeline does not contain any pending transactions, performing the global operation on the l2 cache.
Inventor(s): Naveen Bhoria of Plano TX (US) for texas instruments incorporated, Timothy David Anderson of University Park TX (US) for texas instruments incorporated, Pete Michael Hippleheuser of Murphy TX (US) for texas instruments incorporated
IPC Code(s): G06F12/0891, G06F12/1027
CPC Code(s): G06F12/0891
Abstract: methods, apparatus, systems and articles of manufacture are disclosed to forward and invalidate inflight data in a store queue. an example apparatus includes a cache storage, a cache controller coupled to the cache storage and operable to receive a first memory operation, determine that the first memory operation corresponds to a read miss in the cache storage, determine a victim address in the cache storage to evict in response to the read miss, issue a read-invalidate command that specifies the victim address, compare the victim address to a set of addresses associated with a set of memory operations being processed by the cache controller, and in response to the victim address matching a first address of the set of addresses corresponding to a second memory operation of the set of memory operations, provide data associated with the second memory operation.
Inventor(s): Naveen Bhoria of Plano TX (US) for texas instruments incorporated, Timothy David Anderson of University Park TX (US) for texas instruments incorporated, Pete Michael Hippleheuser of Murphy TX (US) for texas instruments incorporated
IPC Code(s): G06F12/128, G06F9/30, G06F9/54, G06F11/10, G06F12/02, G06F12/0802, G06F12/0804, G06F12/0806, G06F12/0811, G06F12/0815, G06F12/0817, G06F12/0853, G06F12/0855, G06F12/0864, G06F12/0884, G06F12/0888, G06F12/0891, G06F12/0895, G06F12/0897, G06F12/12, G06F12/121, G06F12/126, G06F12/127, G06F13/16, G06F15/80, G11C5/06, G11C7/10, G11C7/22, G11C29/42, G11C29/44
CPC Code(s): G06F12/128
Abstract: methods, apparatus, systems and articles of manufacture to facilitate an atomic operation and/or a histogram operation in cache pipeline are disclosed an example system includes a cache storage coupled to an arithmetic component; and a cache controller coupled to the cache storage, wherein the cache controller is operable to: receive a memory operation that specifies a set of data; retrieve the set of data from the cache storage; utilize the arithmetic component to determine a set of counts of respective values in the set of data; generate a vector representing the set of counts; and provide the vector.
Inventor(s): Naveen BHORIA of Plano TX (US) for texas instruments incorporated, Timothy David ANDERSON of University Park TX (US) for texas instruments incorporated, Pete HIPPLEHEUSER of Murphy TX (US) for texas instruments incorporated
IPC Code(s): G06F12/128, G06F9/30, G06F9/54, G06F11/10, G06F12/02, G06F12/0802, G06F12/0804, G06F12/0806, G06F12/0811, G06F12/0815, G06F12/0817, G06F12/0853, G06F12/0855, G06F12/0864, G06F12/0884, G06F12/0888, G06F12/0891, G06F12/0895, G06F12/0897, G06F12/12, G06F12/121, G06F12/126, G06F12/127, G06F13/16, G06F15/80, G11C5/06, G11C7/10, G11C7/22, G11C29/42, G11C29/44
CPC Code(s): G06F12/128
Abstract: a caching system including a first sub-cache, and a second sub-cache coupled in parallel with the first sub-cache; wherein the second sub-cache includes line type bits configured to store an indication that a corresponding line of the second sub-cache is configured to store write-miss data.
Inventor(s): Uri WEINRIB of Mazkeret Batya (IL) for texas instruments incorporated, Barak CHERCHES of Ramat Ha'Kovesh (IL) for texas instruments incorporated, Clive David BITTLESTONE of Allen TX (US) for texas instruments incorporated
IPC Code(s): G06F21/56, G06F21/52
CPC Code(s): G06F21/566
Abstract: a method includes programming first and second values and a first compare enable command into respective first operand, second operand, and first compare enable command registers in a hardware comparator circuit. the method includes determining that a first match exists corresponding to the first and second values, programming a third value into the first operand register and a fourth value into the second operand register, and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit. in response to a determination that a second match exists corresponding to the third and fourth values, the method includes asserting a success interrupt signal, programming a fifth value into the first operand register and a sixth value into the second operand register and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit.
Inventor(s): Jonathan Bergsagel of Dallas TX (US) for texas instruments incorporated, Rajesh Kumar Vanga of Bangalore (IN) for texas instruments incorporated, Venkateswara Rao Mandela of Bangalore (IN) for texas instruments incorporated, Gregory Shurtz of Sugar Land TX (US) for texas instruments incorporated, Nishanth Menon of Dallas TX (US) for texas instruments incorporated
IPC Code(s): G06F21/57, G06F11/22
CPC Code(s): G06F21/575
Abstract: in described examples, a method of operating a system on chip (soc) includes the following steps. receive a component description that describes connections among circuit elements of the soc. receive a list of specified peripherals to activate while the soc boots. receive a hint data that describes a bypass mode clock frequency of a phase locked loop (pll) of the soc. determine an operational data in response to the component description, the hint data, and the specified peripherals. the operational data specifies a subset of the circuit elements required to make the specified peripherals operational. initialize, and limit the initializing, to the subset of the circuit elements.
Inventor(s): Jongwan KIM of Katy TX (US) for texas instruments incorporated
IPC Code(s): G11B27/10, G11B27/034, H04N5/76, H04N5/77, H04N5/775, H04N5/781, H04N9/79, H04N9/82, H04N21/41, H04N21/4223, H04N21/432, H04N21/433, H04N21/438, H04N21/4415, H04N21/442, H04N21/45, H04N21/472, H04N21/482
CPC Code(s): G11B27/105
Abstract: a controller includes a memory, and a processor coupled to the memory. the processor is operable to produce an alternating current (ac) virtual waveform approximately synchronized to an ac voltage of an external device; detect a cessation of the ac voltage; continue to produce the ac virtual waveform during the cessation of the ac voltage; detect a resumption of the ac voltage; apply the ac virtual waveform to a control input of a control function for a period of time in response to detecting the resumption of the ac voltage; and apply an output of a phase-locked loop to the control input instead of the ac virtual waveform after the period of time.
Inventor(s): Avishek Biswas of DALLAS TX (US) for texas instruments incorporated, Mahesh Madhukar Mehendale of GARLAND TX (US) for texas instruments incorporated, Hetul Sanghvi of MURPHY TX (US) for texas instruments incorporated
IPC Code(s): G11C11/4094, G06G7/16, G06N3/065, G11C5/06, G11C7/10, G11C11/4074, G11C11/4097, G11C11/4099, G11C11/54
CPC Code(s): G11C11/4094
Abstract: a device includes a first bit cell, a second bit cell, and a multiply and average (mav) circuit. the mav circuit includes a first selection circuit and a second selection circuit. the first selection circuit has a first selection input and coupled to first and second capacitor terminals, and the first selection circuit is configured to, responsive to a state of the first selection input, set respective states of the first and second capacitor terminals based on a state of the first bit cell. the second selection circuit has a second selection input and is coupled to the first and second capacitor terminals. the second selection circuit is configured to, responsive to a state of the second selection input, set the respective states of the first and second capacitor terminals based on a state of the second bit cell.
Inventor(s): Vivek Swaminathan SRIDHARAN of Dallas TX (US) for texas instruments incorporated, Christopher Daniel MANACK of Flower Mound TX (US) for texas instruments incorporated, Joseph LIU of Plano TX (US) for texas instruments incorporated
IPC Code(s): H01L23/00
CPC Code(s): H01L24/05
Abstract: in some examples, a chip scale package (csp) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. the csp also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns. the csp further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. the second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.
20250030206. CONNECTOR CORROSION MITIGATION_simplified_abstract_(texas instruments incorporated)
Inventor(s): Deric Wayne WATERS of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H01R13/66, G06F13/40
CPC Code(s): H01R13/6683
Abstract: in some examples, an integrated circuit (ic) is configured to detect, by the ic, a presence of liquid in an electrical connector. the ic is also configured to, responsive to the presence of liquid in the electrical connector, remove a bias voltage from at least some conductors of the electrical connector. the ic is also configured to monitor a bus voltage of the electrical connector. the ic is also configured to, based on a value of the bus voltage determined via the monitoring, perform a mitigation action responsive to the presence of liquid in the electrical connector.
20250030328. ADAPTIVE BURST MODE CONTROL_simplified_abstract_(texas instruments incorporated)
Inventor(s): Aki Li of MAOMING CITY (CN) for texas instruments incorporated, Desheng Guo of SHANGHAI (CN) for texas instruments incorporated, Chen Jiang of SUGAR LAND TX (US) for texas instruments incorporated, Qing Ye of KATY TX (US) for texas instruments incorporated
IPC Code(s): H02M1/00, H02M1/088, H02M3/335
CPC Code(s): H02M1/0035
Abstract: in described examples, a device includes a pulse width modulation (pwm) control circuit and a burst mode logic circuit. an input of the burst mode logic circuit is coupled to an output of the pwm control circuit. the burst mode logic circuit is configured to receive a feedback signal from a secondary side of a power conversion circuit. the burst mode logic circuit is configured to suppress a sleep period of a burst mode in response to a magnitude of the feedback signal exceeding a nominal load threshold voltage. the pwm control circuit continues to operate in the burst mode while the burst mode logic circuit suppresses the sleep period.
Inventor(s): Vysakh K of Kerala (IN) for texas instruments incorporated, Shagun Dusad of Bangalore (IN) for texas instruments incorporated, Rajendrakumar Joish of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03F3/45
CPC Code(s): H03F3/45192
Abstract: a cascode amplifier including an amplifier transistor, a cascode transistor, and a current injection circuit. the amplifier transistor has a first current terminal receiving a first power supply voltage, a second current terminal, and a control terminal receiving an input signal. the cascode transistor has a first current terminal coupled to the second current terminal of the amplifier transistor, a second current terminal coupled to an output terminal; and a control terminal receiving a bias voltage. the current injection circuit has an input receiving the input signal, and first and second outputs coupled to the first and second current terminals of the cascode transistor, respectively. the current injection circuit is configured to present out-of-phase currents to the cascode transistor responsive to the input signal.
Inventor(s): Laxmi Vivek TRIPURARI of Bangalore (IN) for texas instruments incorporated, Anand SUBRAMANIAN of Bangalore (IN) for texas instruments incorporated, Tanmay HALDER of Bangalore (IN) for texas instruments incorporated, Anand KANNAN of Bangalore (IN) for texas instruments incorporated, Priyanshu PANDEY of New Delhi (IN) for texas instruments incorporated
IPC Code(s): H03G3/34, H03F3/183, H04R3/00
CPC Code(s): H03G3/34
Abstract: in some examples, a circuit includes a first transistor having a control terminal and first and second terminals. the circuit also includes a first capacitor having first and second terminals, the first terminal of the first capacitor coupled to the control terminal of the first transistor and the second terminal of the first capacitor coupled to the second terminal of the first transistor. the circuit also includes a first switch having first and second terminals, the second terminal of the first switch coupled to the control terminal of the first transistor. the circuit also includes a second capacitor having first and second terminals, the first terminal of the second capacitor coupled to the first terminal of the first transistor and the second terminal of the second capacitor coupled to the first terminal of the first switch.
Inventor(s): Anant Kamath of Bangalore (IN) for texas instruments incorporated, Taisuke Kazama of Plano TX (US) for texas instruments incorporated, Sombuddha Chakraborty of Redwood City CA (US) for texas instruments incorporated
IPC Code(s): H03K17/06, H03K17/687
CPC Code(s): H03K17/063
Abstract: an integrated circuit is provided which comprises a transistor and a driver coupled to a gate of the transistor. in at least one example, the driver controls an operation of the transistor, wherein the driver is operable in a first configuration as a low-side gate driver for a voltage regulator, and wherein the transistor is operable in the first configuration as a low-side switch for the voltage regulator. in at least one example, the driver is operable in a second configuration as a high-side gate driver for the voltage regulator, and wherein the transistor is operable in the second configuration as a high-side switch for the voltage regulator.
Inventor(s): Marius Moe of FETSUND (NO) for texas instruments incorporated, Hagen Graf of OSLO (NO) for texas instruments incorporated, Tarjei Aaberge of NESOYA (NO) for texas instruments incorporated
IPC Code(s): H03L7/093, H03L7/089, H03L7/099
CPC Code(s): H03L7/093
Abstract: a circuit for a phase-locked loop is described herein. the circuit includes a phase frequency detector configured to determine a phase error, a loop filter coupled to the phase frequency detector and configured to provide a clock control signal based on the phase error, and a controller coupled to the phase frequency detector and to the loop filter. the controller is configured to receive the phase error, detect a behavior of the phase error, and, responsive to the behavior of the phase error, perform a response that includes causing the phase frequency detector to adjust the phase error and causing the loop filter to adjust the clock control signal. thus, the circuit may reduce settling time, overshoot, and/or undershoot in an output clock generated based on the clock control signal.
Inventor(s): Jyoti Raj of Bangalore (IN) for texas instruments incorporated, Anand Subramanian of Bangalore (IN) for texas instruments incorporated, Anand Kannan of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03M1/06
CPC Code(s): H03M1/0604
Abstract: in described examples, an integrated circuit (ic) includes first and second integrators, first and second weighted summers, first and second digital-to-analog converters (dacs), and a quantizer. first and second inputs of the first weighted summer are respectively connected to an output of the first integrator and an output of the second dac. an input of the second integrator is connected to an output of the first weighted summer. an input of the second weighted summer is connected to an output of the second integrator. an input of the quantizer is connected to an output of the second weighted summer. inputs of the first and second dacs are connected to respective outputs of the quantizer. an output of the first dac is connected to a first input of the first integrator. a second input of the first integrator and a third input of the first weighted summer are analog signal inputs.
Inventor(s): Tanmay HALDER of Bangalore (IN) for texas instruments incorporated, Anand SUBRAMANIAN of Bangalore (IN) for texas instruments incorporated, Anand KANNAN of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03M1/08
CPC Code(s): H03M1/08
Abstract: in some examples, a circuit includes a first integrator having an input and an output. the circuit also includes a switching architecture having first and second terminals, the first terminal of the switching architecture coupled to the output of the first integrator. the circuit also includes a second integrator having an input and an output, the input of the second integrator coupled to the second terminal of the switching architecture. the circuit also includes a quantizer having an input and an output, the input of the quantizer coupled to the output of the second integrator. the circuit also includes a digital processing circuit having an input and an output, the input of the digital processing circuit coupled to the output of the quantizer.
Inventor(s): Anand SUBRAMANIAN of BANGALORE (IN) for texas instruments incorporated, Tanmay HALDER of BANGALORE (IN) for texas instruments incorporated, Deepa NAIR J S of BENGALURU (IN) for texas instruments incorporated, Sreeja CHAKINGAL of BANGALORE (IN) for texas instruments incorporated
IPC Code(s): H03M3/00
CPC Code(s): H03M3/324
Abstract: in a described example, a circuit includes a digital-to-analog converter (dac) unit element switch circuit including first and second sign switch inputs, first and second select switch inputs, and first, second and third dac outputs. synchronizer logic includes a selection input and first and second synchronization outputs, in which the first synchronization output is coupled to the first select switch input and the second synchronization output is coupled to the second select switch input. selection logic includes a data input, a sign control output and a selection control output, in which the sign control output is coupled to the first and second sign switch inputs, and the selection control output is coupled to the selection input.
Inventor(s): Chunhua HU of Plano TX (US) for texas instruments incorporated, Venkateswar Reddy KOWKUTLA of Allen TX (US) for texas instruments incorporated, Eric HANSEN of McKinney TX (US) for texas instruments incorporated, Denis BEAUDOIN of Rowlett TX (US) for texas instruments incorporated, Thomas Anton LEYRER of Geisenhausen (DE) for texas instruments incorporated
IPC Code(s): H04J3/06, H04L7/00
CPC Code(s): H04J3/0658
Abstract: a system on a chip (soc) is configured to support multiple time domains within a time-sensitive networking (tsn) environment. tsn extends ethernet networks to support a deterministic and high-availability communication on layer 2 (data link layer of open system interconnect “osi” model) for time coordinated capabilities such as industrial automation and control applications. processors in a system may have an application time domain separate from the communication time domain. in addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. the soc supports multiple time domains driven by different time masters and graceful time master switching. timing masters may be switched at run-time in case of a failure in the system. software drives the soc to establish communication paths through a sync router to facilitate communication between time providers and time consumers. multiple time sources are supported.
Inventor(s): TOMAS MOTOS of OSLO (NO) for texas instruments incorporated, KHANH TUAN LE of NESBRU (NO) for texas instruments incorporated
IPC Code(s): H04L9/40, G07C9/00, H04L5/16, H04L7/033, H04L67/12, H04W12/122, H04W56/00, H04W84/20
CPC Code(s): H04L63/1433
Abstract: a method of relay-attack resistant communications in a wireless communications system that includes a master wireless device (master) sending a synchronization signal to a slave wireless device (slave). the synchronization signal includes timing information including a common time reference and a timeslot duration for interlocking master communication timeslots for master and slave communication timeslots so that an alternating tx and rx role pattern is provided. the master analyzes slave packet data received from the slave to identify overlaps of a transmission from the master and the slave packet data, and in a case of detecting overlap, suspends communications from master to slave to prevent a relay-attack.
Inventor(s): Gang HUA of Katy TX (US) for texas instruments incorporated, Mihir Narendra MODY of Bengaluru (IN) for texas instruments incorporated, Niraj NANDAN of Plano TX (US) for texas instruments incorporated, Shashank DABRAL of Allen TX (US) for texas instruments incorporated, Rajasekhar Reddy ALLU of Plano TX (US) for texas instruments incorporated, Denis Roland BEAUDOIN of Rowlett TX (US) for texas instruments incorporated
IPC Code(s): H04N23/84, H04N9/67, H04N9/68
CPC Code(s): H04N23/843
Abstract: a technique for image processing, comprising: receiving input image data, wherein the image data is companded into a first bit depth, wherein the image data includes incomplete color values for pixels of the image data, and wherein the image data is associated with a first color space, interpolating the image data to generate color values for the incomplete color values for pixels of the image data, expanding the image data from the first bit depth to a second bit depth, wherein the color values of the expanded image data have a linear dynamic range, and wherein the second bit depth is higher than the first bit depth, converting the color values for pixels of the expanded image data from the first color space to a second color space, and compressing the color values for pixels of the image data to a third bit depth, the third bit depth lower than the second bit depth, and wherein the compressed color values have a nonlinear dynamic range.
Inventor(s): Gang Hua of Katy TX (US) for texas instruments incorporated, Shashank Dabral of Allen TX (US) for texas instruments incorporated, Mihir Narendra Mody of Bangalore (IN) for texas instruments incorporated, Rajasekhar Reddy Allu of Plano TX (US) for texas instruments incorporated, Niraj Nandan of Plano TX (US) for texas instruments incorporated
IPC Code(s): H04N23/88, H04N9/78, H04N23/71, H04N23/741, H04N23/76
CPC Code(s): H04N23/88
Abstract: local automatic white balance (awb) of wide dynamic range (wdr) images is provided. methods and systems include collecting, by an image signal processor (isp), statistics for local awb from at least one wide dynamic range (wdr) image received by the isp; generating, by a processor, based on the statistics, local gain lookup tables (luts), one for each color channel represented in the wdr image(s), each local gain lut providing a correlation between gain and intensity; and storing the local gain luts. further processing includes, for each of multiple pixels of a wdr image to be output calculating an intensity value, accessing the local gain lut for the color channel corresponding to that pixel using the calculated intensity value to identify a corresponding local gain value, and applying the local gain value to that pixel.
Inventor(s): Pushpa Mahalingam of Richardson TX (US) for texas instruments incorporated, Alexei Sadovnikov of Sunnyvale CA (US) for texas instruments incorporated
IPC Code(s): H01L27/092, H01L21/265, H01L21/266, H01L21/8238
CPC Code(s): H01L27/0928
Abstract: a microelectronic device including an analog mos transistor. the analog transistor has a body well having a first conductivity type in a semiconductor material of a substrate of the microelectronic device. the body well extends deeper in the substrate than a field relief dielectric layer at the top surface of the semiconductor material. the analog transistor has a drain well and a source well having a second, opposite, conductivity type in the semiconductor material, both contacting the body well. the drain well and the source well extend deeper in the substrate than the field relief dielectric layer. the analog transistor has a gate on a gate dielectric layer over the body well. the drain well and the source well extend partway under the gate at the top surface of the semiconductor material.
TEXAS INSTRUMENTS INCORPORATED patent applications on January 23rd, 2025
- TEXAS INSTRUMENTS INCORPORATED
- G01R31/3185
- G01R31/317
- CPC G01R31/318552
- Texas instruments incorporated
- G05F1/565
- CPC G05F1/565
- G06F3/06
- CPC G06F3/0653
- G06F9/46
- G06F9/30
- G06F9/38
- G06F9/448
- G06F9/48
- G06F9/54
- G06F11/30
- G06F12/0804
- G06F12/0811
- G06F12/0813
- G06F12/0817
- G06F12/0831
- G06F12/0855
- G06F12/0871
- G06F12/0888
- G06F12/0891
- G06F12/12
- G06F12/121
- G06F13/16
- CPC G06F9/467
- G06F12/1027
- CPC G06F12/0891
- G06F12/128
- G06F11/10
- G06F12/02
- G06F12/0802
- G06F12/0806
- G06F12/0815
- G06F12/0853
- G06F12/0864
- G06F12/0884
- G06F12/0895
- G06F12/0897
- G06F12/126
- G06F12/127
- G06F15/80
- G11C5/06
- G11C7/10
- G11C7/22
- G11C29/42
- G11C29/44
- CPC G06F12/128
- G06F21/56
- G06F21/52
- CPC G06F21/566
- G06F21/57
- G06F11/22
- CPC G06F21/575
- G11B27/10
- G11B27/034
- H04N5/76
- H04N5/77
- H04N5/775
- H04N5/781
- H04N9/79
- H04N9/82
- H04N21/41
- H04N21/4223
- H04N21/432
- H04N21/433
- H04N21/438
- H04N21/4415
- H04N21/442
- H04N21/45
- H04N21/472
- H04N21/482
- CPC G11B27/105
- G11C11/4094
- G06G7/16
- G06N3/065
- G11C11/4074
- G11C11/4097
- G11C11/4099
- G11C11/54
- CPC G11C11/4094
- H01L23/00
- CPC H01L24/05
- H01R13/66
- G06F13/40
- CPC H01R13/6683
- H02M1/00
- H02M1/088
- H02M3/335
- CPC H02M1/0035
- H03F3/45
- CPC H03F3/45192
- H03G3/34
- H03F3/183
- H04R3/00
- CPC H03G3/34
- H03K17/06
- H03K17/687
- CPC H03K17/063
- H03L7/093
- H03L7/089
- H03L7/099
- CPC H03L7/093
- H03M1/06
- CPC H03M1/0604
- H03M1/08
- CPC H03M1/08
- H03M3/00
- CPC H03M3/324
- H04J3/06
- H04L7/00
- CPC H04J3/0658
- H04L9/40
- G07C9/00
- H04L5/16
- H04L7/033
- H04L67/12
- H04W12/122
- H04W56/00
- H04W84/20
- CPC H04L63/1433
- H04N23/84
- H04N9/67
- H04N9/68
- CPC H04N23/843
- H04N23/88
- H04N9/78
- H04N23/71
- H04N23/741
- H04N23/76
- CPC H04N23/88
- H01L27/092
- H01L21/265
- H01L21/266
- H01L21/8238
- CPC H01L27/0928
