TEXAS INSTRUMENTS INCORPORATED patent applications on February 20th, 2025
Patent Applications by TEXAS INSTRUMENTS INCORPORATED on February 20th, 2025
TEXAS INSTRUMENTS INCORPORATED: 15 patent applications
TEXAS INSTRUMENTS INCORPORATED has applied for patents in the areas of G06F9/38 (2), H01L29/66 (2), H03K19/0185 (2), H01L29/20 (2), H03F3/45 (2) H01L29/7786 (2), B60L7/14 (1), G01S7/0232 (1), G06F3/0604 (1), G06F3/0622 (1)
With keywords such as: output, input, coupled, circuit, terminal, comparator, sao, resistor, region, and current in patent application abstracts.
Patent Applications by TEXAS INSTRUMENTS INCORPORATED
Inventor(s): Aravind Samba Murthy of Atlanta GA (US) for texas instruments incorporated, David Patrick Magee of Allen TX (US) for texas instruments incorporated
IPC Code(s): B60L7/14, B60L7/18, B60L15/02, B60L15/20, H02P3/16, H02P21/22, H02P21/36, H02P27/08
CPC Code(s): B60L7/14
Abstract: a regenerative braking controller for an ac motor. to determine an electromagnetic torque for slowing or stopping the motor, the regenerative braking controller accesses a lookup table to retrieve a braking torque value corresponding to a current estimate of rotor velocity. the retrieved braking torque may correspond to a maximum or minimum torque level at which regenerative braking will occur at the current rotor velocity, or to a torque level at which charging current during regenerative braking will be maximized. if an external mechanical brake is present, the regenerative braking controller can forward an external braking torque signal to a controller so that the mechanical brake can apply the remainder of the braking force beyond that indicated by the regenerative braking torque. a method for establishing the braking torques to be stored in the lookup table is also disclosed.
Inventor(s): Anil Varghese MANI of Bangalore (IN) for texas instruments incorporated, Sandeep RAO of Bangalore (IN) for texas instruments incorporated, Dan WANG of Allen TX (US) for texas instruments incorporated
IPC Code(s): G01S7/02, G01S13/58
CPC Code(s): G01S7/0232
Abstract: radar systems, radar-implementation methods, and non-transitory processor-readable mediums storing processor-executable instructions for implementing radar chirp generation and processing are provided. an example set of processor-executable instructions includes instructions for configuring each of a plurality of transmitters to transmit each chirp of a set of chirps with a specific spin frequency that is different for each transmitter, in which the specific spin frequency is a function of an index value identifying the corresponding transmitter, and a number of the plurality of transmitters; and determining, in a frequency domain, a doppler representation based on reflected signals that are reflected from one or more objects contacted by one or more chirps of the transmitted sets of chirps, in which the doppler representation includes multiple spectrum bands including one or more empty spectrum bands determined by the specific spin frequency function, wherein none of the object(s) appear(s) in any of the empty spectrum band(s).
Inventor(s): Kai CHIRCA of Dallas TX (US) for texas instruments incorporated, Matthew David PIERSON of Frisco TX (US) for texas instruments incorporated
IPC Code(s): G06F3/06, G06F9/30, G06F9/38, G06F9/48, G06F9/50, G06F12/06, G06F12/0811, G06F12/0815, G06F12/0817, G06F12/0831, G06F12/084, G06F12/0846, G06F12/0855, G06F12/0862, G06F12/0875, G06F12/0891, G06F12/10, G06F12/1009, G06F13/12, G06F13/16, G06F13/40, H03M13/01, H03M13/09, H03M13/15, H03M13/27
CPC Code(s): G06F3/0604
Abstract: a device includes a memory bank. the memory bank includes data portions of a first way group. the data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. the memory bank further includes data portions of a second way group. the device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.
Inventor(s): Prasanth Viswanathan Pillai of Bangalore (IN) for texas instruments incorporated, David Foley of Sugar Land TX (US) for texas instruments incorporated, Rajasekhar Allu of Plano TX (US) for texas instruments incorporated, Amrit Mundra of Allen TX (US) for texas instruments incorporated, Patrick Kruse of Richmond TX (US) for texas instruments incorporated
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0622
Abstract: methods, apparatus, systems, and articles of manufacture are described to facilitate access control in memory. an example method includes accessing state values stored in non-volatile memory, the state values corresponding to a state of the non-volatile memory; responsive to obtaining a request to enter a diagnostic mode, authenticating credentials corresponding to the request; determining the state of the non-volatile memory based on the state values; and determining whether to permit or prohibit access to the non-volatile memory based on the determined state.
20250060965. CONDITIONAL BRANCH INSTRUCTIONS_simplified_abstract_(texas instruments incorporated)
Inventor(s): Alexander Tessarolo of Lindfield (AU) for texas instruments incorporated, Venkatesh Natarajan of Bangalore (IN) for texas instruments incorporated, Alan Davis of Sugar Land TX (US) for texas instruments incorporated
IPC Code(s): G06F9/38, G06F9/30
CPC Code(s): G06F9/3804
Abstract: various embodiments of the present disclosure relate to conditional branch instructions to support software pipelining techniques. in an example embodiment, a system including instruction fetch circuitry, decoder circuitry, and conditional branch circuitry is provided. the instruction fetch circuitry is configured to fetch a conditional branch instruction from memory and provide the instruction to the decoder circuitry. the instruction includes an iteration count and multiple branch destinations. the branch destinations include two or more branch destinations corresponding to conditions against which the conditional branch circuitry evaluates the iteration count. the decoder circuitry is configured to cause the conditional branch circuitry to select a branch destination, of the two or more branch destinations, based on a comparison of the iteration count to each of the conditions and cause the instruction fetch circuitry to fetch an indication of an instruction from a memory location stored at the selected branch destination.
Inventor(s): Ramakrishnan Venkatraman of BENGALURU (IN) for texas instruments incorporated, Vikram Gakhar of BANGALORE (IN) for texas instruments incorporated, Nischal R of CHIKKABALLAPUR (IN) for texas instruments incorporated, Amrutheshwara Rao KV of BANGALORE (IN) for texas instruments incorporated, Madhura Nasare of MUMBAI (IN) for texas instruments incorporated, Naman Bafna of BALAGHAT (IN) for texas instruments incorporated
IPC Code(s): H02M1/088, H02M3/158
CPC Code(s): H02M1/088
Abstract: described embodiments include a control circuit with a first comparator having a first comparator input receiving a first threshold voltage, and a second comparator input coupled to an output voltage terminal. a second comparator has a third comparator input receiving a second threshold voltage, and a fourth comparator input coupled to a current output terminal. a first logic circuit provides a true signal at its output responsive to a particular number of its inputs receiving a true input. a second logic circuit has inputs coupled to the first comparator output, and to the first logic output. a variable resistance circuit has an output coupled to a mode detection output. an amplifier has inputs coupled to the variable resistance circuit output, and a third reference voltage source. a duty cycle generation circuit provides a respective pulse width modulation (pwm) signal at each of its respective duty cycle outputs.
20250062685. LOW NOISE CHARGE PUMP CIRCUIT_simplified_abstract_(texas instruments incorporated)
Inventor(s): Tuomas TUIKKANEN of Oulu (FI) for texas instruments incorporated, Markus SILJANDER of Oulu (FI) for texas instruments incorporated, Mikko LOIKKANEN of Oulu (FI) for texas instruments incorporated
IPC Code(s): H02M3/07, H03K19/0185
CPC Code(s): H02M3/07
Abstract: a charge pump circuit includes first and second capacitors, first, second, third and fourth switches, and a transistor. the first switch is coupled between a top plate of the first capacitor and a first voltage input terminal. the second switch is coupled between a bottom plate of the first capacitor and a reference voltage terminal. the third switch is coupled between the top plate of the first capacitor and a top plate of the second capacitor. the transistor and the fourth switch are coupled in series between the bottom plate of the first capacitor and a second voltage input terminal.
Inventor(s): Rohit Narula of Bangalore (IN) for texas instruments incorporated, Vikram Gakhar of Bangalore (IN) for texas instruments incorporated, Preetam Tadeparthy of Bangalore (IN) for texas instruments incorporated, Nischal R. of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H02M3/335, G01R19/165
CPC Code(s): H02M3/335
Abstract: some examples relate to a circuit including a plurality of input pins, a plurality of output pins, a pulse width modulated (pwm) controller, and an inductor-open detection circuit. the pwm controller has a plurality of inputs and a plurality of outputs. the plurality of inputs of the pwm controller are coupled to the plurality of input pins, and the plurality of outputs of the pwm controller are coupled to the plurality of output pins. the inductor-open detection circuit has an input coupled to a pin of the plurality of input pins, and has an output coupled to the pwm controller.
Inventor(s): Mohamed Ahmed of Merrimack NH (US) for texas instruments incorporated, Matthew Schurmann of Wylie TX (US) for texas instruments incorporated, Preetam Tadeparthy of Bangalore (IN) for texas instruments incorporated, Rohit Narula of Bangalore (IN) for texas instruments incorporated, Vikram Gakhar of Bangalore (IN) for texas instruments incorporated, Vikas Lakhanpal of Bilaspur (IN) for texas instruments incorporated, Karthik Anyam of Bangalore (IN) for texas instruments incorporated, Rengang Chen of Center Valley PA (US) for texas instruments incorporated
IPC Code(s): H02M7/537
CPC Code(s): H02M7/537
Abstract: a power controller comprises a control loop configured to control timing of pulsed signals that activate phases of a coupled inductor voltage regulator based on current demand of a load circuit and comprises a transient detection circuit configured to determine a projected current through a compensation inductor of the coupled inductor voltage regulator based on a state of the phases and operating parameters of the coupled inductor voltage regulator. the transient detection circuit is configured to detect a transient in the current demand of the load circuit based on a variability in phase-to-phase overlap of the pulsed signals. responsive to detecting the transient, the transient detection circuit is configured to apply a correction to the control loop that alters the timing of the pulsed signals based on the projected current through the compensation inductor.
Inventor(s): Ahmed Essam HASHIM of GILBERT AZ (US) for texas instruments incorporated, Jose VIDAL of PHOENIX AZ (US) for texas instruments incorporated
IPC Code(s): H03B5/12, H03F3/45
CPC Code(s): H03B5/1253
Abstract: a circuit includes an error amplifier including a reference input, a feedback input, and an error output. a compensation network has a frequency input and a compensation output, in which the compensation output is coupled to the error output. the compensation network configured to provide a variable capacitance between the compensation output and a ground terminal based on a frequency signal at the frequency input having a value representative of a frequency of a clock signal.
Inventor(s): Rohit Chatterjee of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03F3/68, H03F3/195, H03F3/24, H03F3/45, H03F3/72
CPC Code(s): H03F3/68
Abstract: methods, systems, and apparatus are disclosed for coupling a power amplifier input signal. an example system a first amplifier including a signal input, a feedback input, and a differential output that includes a first output and a second output, a first resistor including a first resistor terminal and a second resistor terminal, wherein the first resistor terminal is coupled to the first output, a second resistor including a third resistor terminal and a fourth resistor terminal, wherein the third resistor terminal is coupled to the second resistor terminal at an output common mode node and the fourth resistor terminal coupled to the second output, and a second amplifier including a first input and a third output, wherein the first input is coupled to the second resistor terminal and third resistor terminal, and the third output is coupled to the feedback input of the first amplifier.
20250062766. CONTINUOUS SIGNAL LEVEL SHIFTER_simplified_abstract_(texas instruments incorporated)
Inventor(s): Kyoung Min Lee of Cary NC (US) for texas instruments incorporated, Satish Vemuri of Raleigh NC (US) for texas instruments incorporated
IPC Code(s): H03K19/0185, H03K5/24
CPC Code(s): H03K19/018528
Abstract: a driver includes a current generator having an input and first and second outputs. the current generator generates a first current at the first output while a signal at the input is at a first logic state and generates a second current at the second output while the signal at the input is at a second logic state. a comparator has a first comparator input, a second comparator input, and a first comparator output, and a second comparator output. the first comparator input is coupled to the first output, and the second comparator input is coupled to the second output. a latch has a first latch input, a second latch input, and a latch output. the first latch input is coupled to the first comparator output, and the second latch input is coupled to the second comparator output. a gate control circuit has an input coupled to the latch output.
Inventor(s): Vivienne Sze of Cambridge MA (US) for texas instruments incorporated, Madhukar Budagavi of Plano TX (US) for texas instruments incorporated, Woo-Shik Kim of San Diego CA (US) for texas instruments incorporated, Do-Kyoung Kwon of Allen TX (US) for texas instruments incorporated, Minhua Zhou of San Diego CA (US) for texas instruments incorporated
IPC Code(s): H04N19/86, H04N19/117, H04N19/463, H04N19/70, H04N19/80, H04N19/82, H04N19/91
CPC Code(s): H04N19/86
Abstract: a method for sample adaptive offset (sao) filtering and sao parameter signaling in a video encoder is provided that includes determining sao parameters for largest coding units (lcus) of a reconstructed picture, wherein the sao parameters include an indicator of an sao filter type and a plurality of sao offsets, applying sao filtering to the reconstructed picture according to the sao parameters, and entropy encoding lcu specific sao information for each lcu of the reconstructed picture in an encoded video bit stream, wherein the entropy encoded lcu specific sao information for the lcus is interleaved with entropy encoded data for the lcus in the encoded video bit stream. determining sao parameters may include determining the lcu specific sao information to be entropy encoded for each lcu according to an sao prediction protocol.
Inventor(s): Dong Seup LEE of McKinney TX (US) for texas instruments incorporated, Jungwoo JOH of Allen TX (US) for texas instruments incorporated, Pinghai HAO of Plano TX (US) for texas instruments incorporated, Sameer PENDHARKAR of Allen TX (US) for texas instruments incorporated
IPC Code(s): H01L29/778, H01L21/265, H01L29/06, H01L29/08, H01L29/20, H01L29/417, H01L29/423, H01L29/66
CPC Code(s): H01L29/7786
Abstract: in some examples, a transistor comprises a gallium nitride (gan) layer; a gan-based alloy layer having a top side and disposed on the gan layer, wherein source, drain, and gate contact structures are supported by the gan layer, and a first doped region positioned in a drain access region and extending from the top side into the gan layer.
Inventor(s): Tatsuya Tominari of Plano TX (US) for texas instruments incorporated, Nicholas Stephen Dellas of Dallas TX (US) for texas instruments incorporated, Qhalid Fareed of Plano TX (US) for texas instruments incorporated
IPC Code(s): H01L29/778, H01L29/04, H01L29/20, H01L29/205, H01L29/66
CPC Code(s): H01L29/7786
Abstract: a semiconductor device includes a gan fet on a silicon substrate and a buffer layer of iii-n semiconductor material, with a columnar region, a transition region surrounding the columnar region, and an inter-columnar region around the transition region. the columnar region is higher than the inter-columnar region. the gan fet includes a gate of iii-n semiconductor material with a thickness greater than twice the vertical range of the top surface of the buffer layer in the columnar region. a difference between the gate thickness over the columnar region and over the transition region is less than half of the vertical range of the top surface of the buffer layer in the columnar surface. the semiconductor device may be formed by forming a gate layer of iii-n semiconductor material over the barrier layer by a gate movpe process using a carrier gas that includes zero to 40 percent hydrogen gas.
TEXAS INSTRUMENTS INCORPORATED patent applications on February 20th, 2025
- TEXAS INSTRUMENTS INCORPORATED
- B60L7/14
- B60L7/18
- B60L15/02
- B60L15/20
- H02P3/16
- H02P21/22
- H02P21/36
- H02P27/08
- CPC B60L7/14
- Texas instruments incorporated
- G01S7/02
- G01S13/58
- CPC G01S7/0232
- G06F3/06
- G06F9/30
- G06F9/38
- G06F9/48
- G06F9/50
- G06F12/06
- G06F12/0811
- G06F12/0815
- G06F12/0817
- G06F12/0831
- G06F12/084
- G06F12/0846
- G06F12/0855
- G06F12/0862
- G06F12/0875
- G06F12/0891
- G06F12/10
- G06F12/1009
- G06F13/12
- G06F13/16
- G06F13/40
- H03M13/01
- H03M13/09
- H03M13/15
- H03M13/27
- CPC G06F3/0604
- CPC G06F3/0622
- CPC G06F9/3804
- H02M1/088
- H02M3/158
- CPC H02M1/088
- H02M3/07
- H03K19/0185
- CPC H02M3/07
- H02M3/335
- G01R19/165
- CPC H02M3/335
- H02M7/537
- CPC H02M7/537
- H03B5/12
- H03F3/45
- CPC H03B5/1253
- H03F3/68
- H03F3/195
- H03F3/24
- H03F3/72
- CPC H03F3/68
- H03K5/24
- CPC H03K19/018528
- H04N19/86
- H04N19/117
- H04N19/463
- H04N19/70
- H04N19/80
- H04N19/82
- H04N19/91
- CPC H04N19/86
- H01L29/778
- H01L21/265
- H01L29/06
- H01L29/08
- H01L29/20
- H01L29/417
- H01L29/423
- H01L29/66
- CPC H01L29/7786
- H01L29/04
- H01L29/205
