TEXAS INSTRUMENTS INCORPORATED patent applications on December 26th, 2024
Patent Applications by TEXAS INSTRUMENTS INCORPORATED on December 26th, 2024
TEXAS INSTRUMENTS INCORPORATED: 29 patent applications
TEXAS INSTRUMENTS INCORPORATED has applied for patents in the areas of G06F9/48 (3), G06F9/30 (3), G06F9/38 (3), H01L23/00 (2), H01L21/48 (2) G06F13/28 (2), A61M16/024 (1), H01L25/16 (1), H04W40/00 (1), H04W12/0431 (1)
With keywords such as: terminal, data, coupled, voltage, circuitry, surface, circuit, winding, differential, and current in patent application abstracts.
Patent Applications by TEXAS INSTRUMENTS INCORPORATED
Inventor(s): John VARELA MUNOZ of Plano TX (US) for texas instruments incorporated
IPC Code(s): A61M16/00
CPC Code(s): A61M16/024
Abstract: in an example, a system includes a flow element configured to direct a gas flow. the system also includes a temperature sensor coupled to the flow element, the temperature sensor configured to determine a temperature of the gas flow. the system includes a first ultrasonic transducer and a second ultrasonic transducer coupled to the flow element, where the first ultrasonic transducer and the second ultrasonic transducer are configured to determine a time of flight of the gas flow. the system also includes a processor configured to determine a volume concentration of a gas in the gas flow based at least in part of the time of flight and the temperature of the gas flow.
Inventor(s): David P. Magee of Allen TX (US) for texas instruments incorporated, Hailong Chen of Richardson TX (US) for texas instruments incorporated
IPC Code(s): B08B7/02, B06B1/02, B06B1/06, G02B7/02, G02B27/00, H04N23/55
CPC Code(s): B08B7/028
Abstract: methods, apparatus, systems are described in conjunction with a watertight housing designed for ultrasonic lens cleaning. an example apparatus includes a transducer having a surface and an opening; a bracket having a first surface, a second surface, a third surface, and an opening, the first surface of the bracket coupled to the surface of the transducer, the opening of the bracket aligned with the opening of the transducer; and a lens having a first surface and a second surface, the first surface of the lens is coupled to the second surface of the bracket, the second surface of the lens coupled to the third surface of the bracket, the lens covering the opening of the transducer and the opening of the bracket.
Inventor(s): Damian PANTER of Freising (DE) for texas instruments incorporated, Carsten Ingo STOERK of Freising (DE) for texas instruments incorporated, Florian NEVEU of Neufahrn (DE) for texas instruments incorporated
IPC Code(s): G05F1/56
CPC Code(s): G05F1/56
Abstract: in an example, a method includes enabling a first voltage supply and a second voltage supply. the method also includes selecting, with a decision comparator, a selected voltage supply from either the first voltage supply or the second voltage supply based on which of the first voltage supply or the second voltage supply ramps up first. the method includes monitoring the selected voltage supply with the decision comparator. the method also includes, responsive to a voltage from the selected voltage supply dropping below a dropout voltage level of a low dropout regulator, switching to an other voltage supply with the decision comparator.
Inventor(s): Bumkil Lee of Allen TX (US) for texas instruments incorporated, Lei Chen of Plano TX (US) for texas instruments incorporated, Chienyu Huang of Plano TX (US) for texas instruments incorporated
IPC Code(s): G05F1/565, G05F1/575, G05F1/59
CPC Code(s): G05F1/565
Abstract: an example apparatus includes: regulator circuitry having a first terminal and a second terminal; current sense circuitry having a first terminal, a second terminal, and a third terminal; the first terminal of the current sense circuitry coupled to the first terminal of the regulator circuitry, the second terminal of the current sense circuitry coupled to the second terminal of the regulator circuitry; and current limit circuitry including: a transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the third terminal of the current sense circuitry, the control terminal coupled to the second terminal of the regulator circuitry; and current source circuitry having a terminal coupled to the second current terminal of the transistor.
Inventor(s): Yaron Alpert of Hod-Hasharon (IL) for texas instruments incorporated, Yoav Ben-Yehezkel of Netanya (IL) for texas instruments incorporated, Barak Cherches of Ramat-Hakovesh (IL) for texas instruments incorporated
IPC Code(s): G06F8/65
CPC Code(s): G06F8/65
Abstract: a system includes memory which has a first resource at a first physical address space that includes a first physical address, and a second resource at a second physical address space that includes a second physical address. a memory mapper is coupled to the memory. the memory mapper is configured to convert logical addresses to physical addresses. a processor is coupled to the memory mapper. the processor is configured to execute the first resource from a first logical address mapped by the memory mapper to the first physical address. while executing a firmware update resource, the processor can remap the first logical address to the second physical address using the memory mapper and then execute the second resource from the first logical address.
Inventor(s): Alexander Tessarolo of Lindfield (AU) for texas instruments incorporated, Venkatesh Natarajan of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G06F9/30, G06F9/38
CPC Code(s): G06F9/30058
Abstract: various embodiments of the present disclosure relate to the conditional execution of program code. in an example embodiment, a system including instruction fetch circuitry, decoder circuitry, and condition aggregation circuitry is provided. the instruction fetch circuitry is configured to fetch a conditional branch instruction (cbi) from memory which identifies multiple register locations and a condition aggregation operation. the condition aggregation operation is representative of an instruction which identifies multiple conditions to be checked. the instruction fetch circuitry provides the cbi to the decoder circuitry. in response, the decoder circuitry is configured to cause the condition aggregation circuitry to perform the multiple conditions checks with respect to values stored in the multiple register locations.
Inventor(s): Venkatesh Natarajan of Bangalore (IN) for texas instruments incorporated, Alexander Tessarolo of Lindfield (AU) for texas instruments incorporated
IPC Code(s): G06F9/30, G06F9/38
CPC Code(s): G06F9/30196
Abstract: methods, apparatus, systems, and articles of manufacture are described to facilitate unaligned byte stream operations. an example apparatus includes a register including a first portion and a second portion; and a decoder to, responsive to obtaining an instruction, move at least some data from the first portion of the register to the second portion of the register based on an address identified in the instruction; an interface to cause a multiple-byte read to access data from an aligned address of memory; and the decoder to store the accessed data into the first portion of the register based on the address identified in the instruction.
Inventor(s): Alexander Tessarolo of Lindfield (AU) for texas instruments incorporated, Venkatesh Natarajan of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G06F9/38, G06F9/30
CPC Code(s): G06F9/3804
Abstract: various embodiments of the present disclosure relate to the conditional execution of program code. in an example embodiment, a system including instruction fetch circuitry, decoder circuitry, and multi-condition branch circuitry is provided. the instruction fetch circuitry is configured to fetch a multi-condition branch instruction (mcbi) from memory. the mcbi identifies multiple status registers and multiple branch destinations. the multiple status registers of the mcbi are representative of registers which hold results of multiple condition evaluations, such that each status register corresponds to a different one of the multiple condition evaluations. similarly, the multiple branch destinations of the mcbi also correspond to a different one of the multiple condition evaluations. the instruction fetch circuitry provides the mcbi to the decoder circuitry. in response, the decoder circuitry is configured to cause the multi-condition branch circuitry to execute the multi-condition branch instruction.
Inventor(s): Niraj Nandan of Plano TX (US) for texas instruments incorporated, Rajasekhar Reddy Allu of Plano TX (US) for texas instruments incorporated, Brian Chae of Duluth GA (US) for texas instruments incorporated, Mihir Mody of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G06F13/28, G06F9/48, G06F13/16, G06F13/40
CPC Code(s): G06F13/28
Abstract: systems and methods enable data aggregation and pattern adaptation in hardware acceleration subsystems. in an example, a system, which may be a hardware thread scheduling system, includes schedulers, each associated with a pattern adapter; hardware accelerators respectively coupled to the schedulers; load store engines respectively associated with the hardware accelerators; a memory coupled to the load store engines; and a direct memory access (dma) circuit coupled to the memory. each pattern adapter is able to convert data from one format to another, and each load store engine is able to aggregate data elements to form larger data elements to improve overall processing efficiency.
Inventor(s): Mihir Narendra MODY of Bengaluru (IN) for texas instruments incorporated, Ankur ANKUR of New Delhi (IN) for texas instruments incorporated, Vivek Vilas DHANDE of Jalgaon (IN) for texas instruments incorporated, Kedar Satish CHITNIS of Bengaluru (IN) for texas instruments incorporated, Niraj NANDAN of Plano TX (US) for texas instruments incorporated, Brijesh JADAV of Bengaluru (IN) for texas instruments incorporated, Shyam JAGANNATHAN of Bengaluru (IN) for texas instruments incorporated, Prithvi Shankar YEYYADI ANANTHA of Bengaluru (IN) for texas instruments incorporated, Santhanakrishnan Narayanan NARAYANAN of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): G06F13/28, G06F9/48, G06F13/16, G06F13/42, G06F15/78
CPC Code(s): G06F13/28
Abstract: systems and methods in which trace data is efficiently managed are provided. an example system includes a memory, a first interface, and a processing resource communicably coupled to the first interface and to the memory. the processing resource includes a buffer, and a first controller to transmit a set of data from the buffer with associated trace information for the set of data to the memory. a second controller transmits the set of data with the associated trace information from the memory to a second interface.
Inventor(s): Mihir Narendra MODY of Bengaluru (IN) for texas instruments incorporated, Niraj NANDAN of Plano TX (US) for texas instruments incorporated, Ankur ANKUR of New Delhi (IN) for texas instruments incorporated, Mayank MANGLA of Allen TX (US) for texas instruments incorporated, Prithvi Shankar YEYYADI ANANTHA of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): G06T1/20, G06F9/48, G06F11/10, G06T1/60
CPC Code(s): G06T1/20
Abstract: a technique including receiving an image stream for processing; processing the received image stream in a real time mode of operation; outputting an indication that an image processing pipeline has begun processing the received image stream; receiving, in response to the indication, first configuration information associated with test data for testing the image processing pipeline; switching the image processing pipeline to a non-real time mode of operation to process the test data based on the first configuration information during a vertical blanking period of the received image stream; loading the test data from an external memory; switching an input of the image processing pipeline from the image stream to the test data; determining a checksum based on the processed test data; comparing the determined checksum to an expected checksum to determine that the test data was successfully processed; and outputting an indication that the test data was successfully processed.
Inventor(s): Niraj NANDAN of Plano TX (US) for texas instruments incorporated, Rajasekhar Reddy ALLU of Plano TX (US) for texas instruments incorporated, Mihir Narendra MODY of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): G06T1/60, G06F9/50, G06F9/54
CPC Code(s): G06T1/60
Abstract: a lens distortion correction function operates by backmapping output images to the uncorrected, distorted input images. as a vision image processor completes processing on the image data lines needed for the lens distortion correction function to operate on a group of output, undistorted image lines, the lens distortion correction function begins processing the image data. this improves image processing pipeline delays by overlapping the operations. the vision image processor provides output image data to a circular buffer in sram, rather than providing it to dram. the lens distortion correction function operates from the image data in the circular buffer. by operating from the sram circular buffer, access to the dram for the highly fragmented backmapping image data read operations is removed, improving available dram bandwidth. by using a circular buffer, less space is needed in the sram. the improved memory operations further improve the image processing pipeline delays.
20240428434. STRUCTURED LIGHT PROJECTOR_simplified_abstract_(texas instruments incorporated)
Inventor(s): Srikanth Gurrapu of Frisco TX (US) for texas instruments incorporated, Yangxi Wang of Plano TX (US) for texas instruments incorporated, Zhongyan Sheng of Allen TX (US) for texas instruments incorporated
IPC Code(s): G06T7/521, G03B21/00, G06T7/70
CPC Code(s): G06T7/521
Abstract: described examples include an apparatus includes a spatial light modulator configured to receive input light; and modulate the input light, to produce modulated light, where the modulated light has a pixel pattern of dark pixels and bright pixels. the apparatus also includes a diffractive optical element optically coupled to the spatial light modulator, the diffractive optical element configured to: receive the modulated light; and modulate the pixel pattern of dark pixels and bright pixels, to produce a structured light pattern, the structured light pattern having dark regions and bright regions, the bright regions each having the pixel pattern of dark pixels and bright pixels.
Inventor(s): Lorin Paul NETSCH of Allen TX (US) for texas instruments incorporated, Jacek Piotr STACHURSKI of Dallas TX (US) for texas instruments incorporated
IPC Code(s): G10L19/00, G10L19/008, G10L19/038, G10L19/16, G10L19/24, G10L21/038, G11B20/10
CPC Code(s): G10L19/0017
Abstract: a method of encoding samples in a digital signal is provided that includes receiving a frame of n samples of the digital signal, determining l possible distinct data values in the n samples, determining a reference data value in the l possible distinct data values and a coding order of l−1 remaining possible distinct data values, wherein each of the l−1 remaining possible distinct data values is mapped to a position in the coding order, decomposing the n samples into l−1 coding vectors based on the coding order, wherein each coding vector identifies the locations of one of the l−1 remaining possible distinct data values in the n samples, and encoding the l−1 coding vectors.
Inventor(s): Dongbin Hou of Plano TX (US) for texas instruments incorporated, Sombuddha Chakraborty of Redwood City CA (US) for texas instruments incorporated, Kenji Kawano of Nagano (JP) for texas instruments incorporated, Jeffrey Morroni of Parker TX (US) for texas instruments incorporated, Yuki Sato of Saitama-ken (JP) for texas instruments incorporated
IPC Code(s): H01F27/34, H01F27/02, H01F27/24, H01F27/28, H01F41/00, H02M3/158
CPC Code(s): H01F27/346
Abstract: in one example, an apparatus includes a base, a first inductor, and a second inductor. the first inductor is on the base. the first inductor has a first winding extension, a second winding extension, and a first winding coupled between the first winding extension and the second winding extension, in which at least a part of the second winding extension is vertically between at least a part of the first winding extension and the base. also, the second inductor is on the base. the second inductor has a third winding extension, a fourth winding extension, and a second winding coupled between the third winding extension and the fourth winding extension, in which at least a part of the fourth winding extension is vertically between at least a part of the third winding extension and the base, and the second winding is laterally adjacent to the first winding.
Inventor(s): Yee Gin TEA of Bukit Katil (MY) for texas instruments incorporated, Chong Han LIM of Seri Kembangan (MY) for texas instruments incorporated
IPC Code(s): H01L23/495, H01L21/48, H01L21/56, H01L23/00, H01L23/31
CPC Code(s): H01L23/49548
Abstract: in some examples, a semiconductor package comprises a die pad, a semiconductor die on the die pad, and a mold compound covering the die pad and the semiconductor die. the semiconductor package includes a conductive component including a roughened surface, the roughened surface having a roughness ranging from an arithmetic mean surface height (sa) of 1.4 to 3.2. the mold compound is coupled to the roughened surface. the semiconductor package includes a bond wire coupling the semiconductor die to the roughened surface. the bond wire is directly coupled to the roughened surface without a precious metal positioned therebetween.
Inventor(s): Jie CHEN of PLANO TX (US) for texas instruments incorporated, Rajen MURUGAN of DALLAS TX (US) for texas instruments incorporated, Sylvester ANKAMAH-KUSI of MCKINNEY TX (US) for texas instruments incorporated, Harshpreet Singh Phull BAKSHI of DALLAS TX (US) for texas instruments incorporated, Jonathan NOQUIL of PLANO TX (US) for texas instruments incorporated
IPC Code(s): H01L25/16, H01L21/48, H01L23/00, H01L23/13, H01L23/498
CPC Code(s): H01L25/16
Abstract: an example method includes forming a cavity in a multi-layer substrate of a leadframe. the cavity extends from a first substrate surface of the leadframe into the multi-layer substrate to define a cavity floor spaced from the first substrate surface by a cavity sidewall, and at least one conductive terminal is on the cavity floor. the method also includes placing an inductor module in the cavity, in which the inductor module includes a conductor embedded within a dielectric substrate between spaced apart first and second inductor terminals of the inductor module. the method also includes coupling at least one of the first and second inductor terminals to the at least one conductive terminal on the cavity floor. the method also includes encapsulating the inductor module and at least a portion of the leadframe with a mold compound.
Inventor(s): Naveen Tipirneni of Frisco TX (US) for texas instruments incorporated, Maik Peter Kaufmann of Freising (DE) for texas instruments incorporated, Michael Lueders of Freising (DE) for texas instruments incorporated, Jungwoo Joh of Allen TX (US) for texas instruments incorporated
IPC Code(s): H01L27/06, H01L21/8252, H01L29/20, H01L29/66, H01L29/778, H02M3/156, H03K3/037
CPC Code(s): H01L27/0629
Abstract: the present invention provides a capacitor having a first structure made of a metal layer and a second structure made of the same metal layer and a dielectric layer between the first and the second metal structure, wherein the dielectric layer has a relative permittivity greater than 4, in particular greater than 6. it also provides a monolithically integrated circuit including such a capacitor and optionally other components. a method of manufacturing such a capacitor is also provided.
Inventor(s): Abbas Ali of Plano TX (US) for texas instruments incorporated, Rajni J. Aggarwal of Garland TX (US) for texas instruments incorporated, Steven J. Adler of Plano TX (US) for texas instruments incorporated, Eugene C. Davis of McKinney TX (US) for texas instruments incorporated
IPC Code(s): H01L29/06, H01L21/265, H01L21/761, H01L21/762, H01L21/763
CPC Code(s): H01L29/0649
Abstract: an electronic device comprises a semiconductor substrate including majority carrier dopants of a first conductivity type, a semiconductor surface layer including majority carrier dopants of a second conductivity type, field oxide that extends on the semiconductor surface layer, and an isolation structure. the isolation structure includes a trench that extends through the semiconductor surface layer and into one of the semiconductor substrate and a buried layer of the semiconductor substrate, and polysilicon including majority carrier dopants of the second conductivity type, the polysilicon fills the trench to a side of the semiconductor surface layer.
Inventor(s): Ya Ping Chen of Chengdu (CN) for texas instruments incorporated, Yunlong Liu of Beijing (CN) for texas instruments incorporated, Hong Yang of Wylie TX (US) for texas instruments incorporated, Jing Hu of Chengdu (CN) for texas instruments incorporated, Chao Zhuang of Chengdu (CN) for texas instruments incorporated, Peng Li of Chongqing (CN) for texas instruments incorporated, Sheng Pin Yang of Chengdu (CN) for texas instruments incorporated
IPC Code(s): H01L29/40, H01L29/66
CPC Code(s): H01L29/407
Abstract: a method of fabricating a semiconductor device includes etching a first trench and a second trench in an epitaxial layer over a semiconductor and forming a dielectric liner within the trenches. a photoresist layer is formed within the trenches and over the epitaxial layer and given a post-exposure bake at a first temperature. the photoresist layer is then given an adhesion-promoting bake at a greater second temperature; the photoresist layer is then removed from a top portion the trenches, thereby exposing a top portion of the dielectric liner and leaving a remaining portion of the photoresist in a bottom portion of the trenches. the exposed dielectric liner is etched, thereby leaving a remaining portion of the dielectric liner in the top portion of the trenches. the remaining portion of the photoresist is removed and the trenches are filled with a polysilicon layer.
20240429732. RELAY STATUS MONITOR CIRCUIT_simplified_abstract_(texas instruments incorporated)
Inventor(s): Kelvin Le of Dallas TX (US) for texas instruments incorporated, Riccardo Ruffo of Muenchen (DE) for texas instruments incorporated, David Stout of Chico TX (US) for texas instruments incorporated, FNU Nitish of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H02J7/04, B60L53/60
CPC Code(s): H02J7/04
Abstract: a battery charger includes a relay having a first terminal and a second terminal. a capacitor has a first terminal and a second terminal. the first terminal is coupled to the second terminal of the relay. a clamp circuit is coupled to the second terminal of the capacitor. a reference voltage circuit has an output terminal. a comparator has a first comparator input terminal coupled to the second terminal of the capacitor and has a second comparator input terminal coupled to the output terminal of the reference voltage circuit.
Inventor(s): Ting-Li Hsu of Aachen (DE) for texas instruments incorporated, Stefan Herzer of Marzling (DE) for texas instruments incorporated, Qiao Yang of Freising (DE) for texas instruments incorporated
IPC Code(s): H02M3/158, H02M1/088
CPC Code(s): H02M3/158
Abstract: a ground reference circuit to generate a ground reference for a voltage reference circuit includes a resistor coupled in series with a transistor via a current mirror. the resistor is coupled between a ground reference terminal of the voltage reference circuit and a ground terminal of a power converter. the transistor control terminal is configured to receive a pulse width modulation (pwm) control signal having a duty cycle similar to a switching element duty cycle of the power converter. the current mirror circuit is coupled between a current terminal of the transistor and the ground reference terminal. a controller configured to control the switching element duty cycle may include the ground reference circuit, along with the voltage reference circuit, and a pwm circuit configured to determine the switching element duty cycle based on a comparison between a reference voltage provided by the voltage reference circuit and the converter output voltage.
Inventor(s): Isaac Cohen of Dix Hills NY (US) for texas instruments incorporated
IPC Code(s): H02M3/335, H02M1/00
CPC Code(s): H02M3/33507
Abstract: a circuit includes a switching stage including a primary switch and an input controller. the input controller activates the primary switch to conduct a primary current in a primary winding of a transformer in response to a zero amplitude of a switch voltage at a switching terminal, and can deactivate the primary switch to provide a secondary current in a secondary winding of the transformer based on the primary current. the circuit also includes an output stage that provides an output voltage in response to the secondary current. the output stage includes a secondary switch and an output controller. the output controller activates the secondary switch to conduct a request current in the secondary winding in response to ringing of a primary voltage across the primary winding and the output voltage, and deactivates the secondary switch to provide the reflected current in the primary winding based on the request current.
Inventor(s): Ding YAN of Shanghai (CN) for texas instruments incorporated, Fangli GE of Shanghai (CN) for texas instruments incorporated, Luyang HE of Shanghai (CN) for texas instruments incorporated
IPC Code(s): H03K17/16, H03K17/687
CPC Code(s): H03K17/162
Abstract: in some examples, an apparatus includes a transistor, a semiconductor device, a clamp circuit, and a charge circuit. the transistor has a control terminal, a first terminal, and a second terminal. the second terminal is coupled to a first input voltage terminal. the semiconductor device is coupled between the first terminal and an output terminal. the clamp circuit is coupled between the control terminal and a switch terminal. the charge circuit is coupled between a second input voltage terminal and the control terminal.
Inventor(s): Tolga Dinc of Dallas TX (US) for texas instruments incorporated, Swaminathan Sankaran of Allen TX (US) for texas instruments incorporated, Baher Haroun of Allen TX (US) for texas instruments incorporated
IPC Code(s): H04L27/20, H04L5/14
CPC Code(s): H04L27/2071
Abstract: an apparatus includes a controller having differential modulation control outputs and is configured to provide differential modulation signals having a particular frequency at the differential modulation control outputs. a differential modulator circuit is coupled between first differential terminals and second differential terminals. the differential modulator circuit has differential modulation control inputs coupled to the differential modulation control outputs. the differential modulator circuit is configured to: modulate first differential signals at the first differential terminals with the differential modulation signals having the particular frequency, provide the modulated first differential signals at the second differential terminals, modulate second differential signals at the second differential terminals with the differential modulation signals having the particular frequency, and provide the modulated second differential signals at the first differential terminals.
Inventor(s): Naveen Srinivasamurthy of Bangalore (IN) for texas instruments incorporated, Soyeb Nagori of Bangalore (IN) for texas instruments incorporated, Manoj Koul of Allen TX (US) for texas instruments incorporated
IPC Code(s): H04N19/132, H04N19/124, H04N19/126, H04N19/149, H04N19/152, H04N19/157, H04N19/172
CPC Code(s): H04N19/132
Abstract: several methods and systems for encoding pictures associated with video data are disclosed. in an embodiment, a method includes determining by a processing module, whether a picture is to be encoded based on at least one of a skip assessment associated with the picture and an encoding status of a pre-selected number of pictures preceding the picture in an encoding sequence. the method further includes encoding by the processing module, a plurality of rows of video data associated with the picture upon determining that the picture is to be encoded, wherein the plurality of rows are encoded based on a pre-selected maximum encoded picture size.
Inventor(s): Yaron ALPERT of Hod-Hasharon (IL) for texas instruments incorporated, Guy MISHOL of Shoham (IL) for texas instruments incorporated
IPC Code(s): H04W12/0431, H04W12/062
CPC Code(s): H04W12/0431
Abstract: in an embodiment, a method includes: transmitting, by a first device, a first message during a first connection event; receiving, at the first device, a first response to the first message from a second device during the first connection event; receiving, by the first device, a second response to the first message from a third device during the first connection event; and receiving, by the first device, a third response from the second device during the first connection event.
Inventor(s): Leonardo Estevez of Rowlett TX (US) for texas instruments incorporated, Avraham Baum of Giva't Shmuel (IL) for texas instruments incorporated, Benzy Gabay of Palo Alto CA (US) for texas instruments incorporated
IPC Code(s): H04W40/00, H04W84/18
CPC Code(s): H04W40/00
Abstract: a method of operating a mesh network is disclosed (fig. ). the method includes receiving a data frame () having a header with plural addresses (fig. ) and determining that the data frame is not from an access point or a leaf node () of the mesh network. a next recipient address of the plural addresses is removed () when the next recipient is a final destination. the next recipient address is set () when the next recipient of the data frame is not a final destination. the data frame is transmitted () to the next recipient.
Inventor(s): Inbal FARCHY of Be’er-Sheva (IL) for texas instruments incorporated, Yaron ALPERT of Hod-Hasharon (IL) for texas instruments incorporated, Maxim ALTSHUL of Kadima (IL) for texas instruments incorporated, Ariton E. XHAFA of Plano TX (US) for texas instruments incorporated
IPC Code(s): H04W76/14
CPC Code(s): H04W76/14
Abstract: in an example, a system includes an electronic device. the electronic device includes a transceiver and a processor. the processor is configured to set a primary anchor point for a first connection event. the processor is also configured to set a virtual anchor point for a sub-connection event for a second wireless device, where the sub-connection event occurs during the first connection event.
TEXAS INSTRUMENTS INCORPORATED patent applications on December 26th, 2024
- TEXAS INSTRUMENTS INCORPORATED
- A61M16/00
- CPC A61M16/024
- Texas instruments incorporated
- B08B7/02
- B06B1/02
- B06B1/06
- G02B7/02
- G02B27/00
- H04N23/55
- CPC B08B7/028
- G05F1/56
- CPC G05F1/56
- G05F1/565
- G05F1/575
- G05F1/59
- CPC G05F1/565
- G06F8/65
- CPC G06F8/65
- G06F9/30
- G06F9/38
- CPC G06F9/30058
- CPC G06F9/30196
- CPC G06F9/3804
- G06F13/28
- G06F9/48
- G06F13/16
- G06F13/40
- CPC G06F13/28
- G06F13/42
- G06F15/78
- G06T1/20
- G06F11/10
- G06T1/60
- CPC G06T1/20
- G06F9/50
- G06F9/54
- CPC G06T1/60
- G06T7/521
- G03B21/00
- G06T7/70
- CPC G06T7/521
- G10L19/00
- G10L19/008
- G10L19/038
- G10L19/16
- G10L19/24
- G10L21/038
- G11B20/10
- CPC G10L19/0017
- H01F27/34
- H01F27/02
- H01F27/24
- H01F27/28
- H01F41/00
- H02M3/158
- CPC H01F27/346
- H01L23/495
- H01L21/48
- H01L21/56
- H01L23/00
- H01L23/31
- CPC H01L23/49548
- H01L25/16
- H01L23/13
- H01L23/498
- CPC H01L25/16
- H01L27/06
- H01L21/8252
- H01L29/20
- H01L29/66
- H01L29/778
- H02M3/156
- H03K3/037
- CPC H01L27/0629
- H01L29/06
- H01L21/265
- H01L21/761
- H01L21/762
- H01L21/763
- CPC H01L29/0649
- H01L29/40
- CPC H01L29/407
- H02J7/04
- B60L53/60
- CPC H02J7/04
- H02M1/088
- CPC H02M3/158
- H02M3/335
- H02M1/00
- CPC H02M3/33507
- H03K17/16
- H03K17/687
- CPC H03K17/162
- H04L27/20
- H04L5/14
- CPC H04L27/2071
- H04N19/132
- H04N19/124
- H04N19/126
- H04N19/149
- H04N19/152
- H04N19/157
- H04N19/172
- CPC H04N19/132
- H04W12/0431
- H04W12/062
- CPC H04W12/0431
- H04W40/00
- H04W84/18
- CPC H04W40/00
- H04W76/14
- CPC H04W76/14
