TEXAS INSTRUMENTS INCORPORATED patent applications on April 4th, 2024
Patent Applications by TEXAS INSTRUMENTS INCORPORATED on April 4th, 2024
TEXAS INSTRUMENTS INCORPORATED: 41 patent applications
TEXAS INSTRUMENTS INCORPORATED has applied for patents in the areas of H01L23/00 (8), H02M3/158 (8), H02M1/00 (5), H01L27/01 (5), H01L23/66 (4)
With keywords such as: coupled, layer, output, circuit, dielectric, isolation, input, control, element, and lower in patent application abstracts.
Patent Applications by TEXAS INSTRUMENTS INCORPORATED
Inventor(s): Daniel Lee Revier of Seattle WA (US) for texas instruments incorporated, Sean Ping Chang of Richardson TX (US) for texas instruments incorporated, Benjamin Stassen Cook of Los Gatos CA (US) for texas instruments incorporated
IPC Code(s): B29C64/165, B22F10/00, B22F10/14, B22F12/37, B22F12/53, B22F12/55, B22F12/57, B28B1/00, B33Y10/00, B33Y30/00, B33Y70/00, B33Y80/00, H01L21/02, H01L21/288, H01L21/67
Abstract: a layer of additive material is formed in a circular printing area on a substrate using additive sources distributed across a printing zone. the additive sources form predetermined discrete amounts of the additive material. the substrate and the additive sources are rotated with respect to each other around a center of rotation, so that a pattern of the additive material is formed in a circular printing area on the substrate. each additive source receives actuation waveforms at an actuation frequency that is proportional to a distance of the additive source from the center of rotation. the actuation waveforms include formation signals, with a maximum of one formation signal in each cycle of the actuation frequency. the formation signals result in the additive sources forming the predetermined discrete amounts of the additive material on the substrate.
20240110999.MAGNETIC CURRENT SENSOR CALIBRATION_simplified_abstract_(texas instruments incorporated)
Inventor(s): Lei Ding of Plano TX (US) for texas instruments incorporated, Elie Libbos of Champaign IL (US) for texas instruments incorporated, Srinath Ramaswamy of Murphy TX (US) for texas instruments incorporated
IPC Code(s): G01R33/00, G01R33/09
Abstract: in one example, a calibration method includes receiving, from a sensor proximate a first conductor, a sensor signal representing a measurement of a magnetic field produced based on a first current flowing in the first conductor and a second current flowing in a second conductor, the first current including first and second current components having different frequencies, and the second current including third and fourth current components, the third current component phase shifted from, and having the same frequency as, the first current component and the fourth current component having a different frequency from the third current component, determining reference values of the first and second currents, and based on the sensor signal and the reference values of the first and second currents, determining for the sensor, a plurality of coupling coefficients representing magnetic field coupling between the first and second conductors.
20240111001.FLUXGATE MAGNETIC SENSOR_simplified_abstract_(texas instruments incorporated)
Inventor(s): Preetinder Garcha of RICHARDSON TX (US) for texas instruments incorporated, Srinath Ramaswamy of MURPHY TX (US) for texas instruments incorporated, Viola Schaeffer of Freising (DE) for texas instruments incorporated
IPC Code(s): G01R33/04, G01R33/00
Abstract: in some examples, an apparatus comprises a first coil, a second coil, a control circuit, and a processing circuit. the second coil is magnetically coupled to the first coil. the control circuit has a signal output coupled to the first coil, and a control output, and the control circuit configured to: responsive to a state of the control input, select a field strength level from a set of discrete field strength levels; and provide a first signal representing the selected field strength level at the signal output. also, the processing circuit has processing inputs and a processing output, the processing inputs coupled to the second coil, the processing output coupled to the control input, and the processing circuit configured to, responsive to a second signal across the processing inputs, set a state of the processing output representing a polarity of a magnetic field sensed by the second coil.
Inventor(s): Terry Alan Bartlett of Dallas TX (US) for texas instruments incorporated, Stephen Aldridge Shaw of Plano TX (US) for texas instruments incorporated, Vivek Kumar Thakur of Plano TX (US) for texas instruments incorporated
IPC Code(s): F21V8/00, G02B3/00
Abstract: described examples include an apparatus includes a dichroic wedge and a spatial light modulator optically coupled to the dichroic wedge. the apparatus also includes a display optically coupled to the spatial light modulator. the display includes a waveguide having a first side and a second side and a first diffractive optical element on the first side of the waveguide. the display also includes a second diffractive optical element on the first side of the waveguide and a third diffractive optical element on the second side of the waveguide.
Inventor(s): ALAN DAVIS of Sugar Land TX (US) for texas instruments incorporated, VENKATESH NATARAJAN of Bangalore (IN) for texas instruments incorporated, ALEXANDER TESSAROLO of Lindfield (AU) for texas instruments incorporated
IPC Code(s): G06F9/38, G06F7/02
Abstract: a processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. the instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.
Inventor(s): Jeffrey Alan West of Dallas TX (US) for texas instruments incorporated, Byron Lovell Williams of Plano TX (US) for texas instruments incorporated, Kashyap Barot of Bangalore (IN) for texas instruments incorporated, Sreeram N. S. of Bangalore (IN) for texas instruments incorporated, Viresh Chinchansure of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H01F27/32, H01F41/12
Abstract: a microelectronic device includes a galvanic isolation component. the galvanic isolation component includes a lower winding and an upper isolation element over the lower winding. the galvanic isolation component further includes a field suppression structure located interior to the lower winding. the field suppression structure includes a conductive field deflector that is separated from the lower winding by a lateral distance that is half a thickness of the lower winding to twice the thickness of the lower winding. a top surface of the conductive field deflector is substantially coplanar with a bottom surface of the lower winding. the conductive field deflector is electrically connected to a semiconductor material in a substrate. the lower winding is separated from a substrate by a first dielectric layer. the upper isolation element is separated from the lower winding by a second dielectric layer.
20240112858.MICRO DEVICE WITH SHEAR PAD_simplified_abstract_(texas instruments incorporated)
Inventor(s): Jeffrey A West of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H01F41/04, H01F27/28, H01F27/29, H01F27/32
Abstract: an example method includes forming and patterning an etch assist layer on a first dielectric layer such that the etch assist layer is not over a first bond pad; forming and patterning a first photoresist layer on a second patterned conductive layer on the first dielectric, wherein the first photoresist layer is not over the first bond pad and etching the second dielectric layer to a depth of 5 to 15% of a thickness of the first dielectric layer and the second dielectric layer; etching the first dielectric layer and second dielectric layer using a second photoresist layer to a depth of 20 to 25%; and exposing the first bond pad by etching the first dielectric layer using a patterned third photoresist layer, such that an area of the dielectric layer exposed by the third opening adjacent to the bond pad is between 3-5 �m thick.
Inventor(s): Scott Kelly Montgomery of Rowlett TX (US) for texas instruments incorporated, James Todd of Plano TX (US) for texas instruments incorporated, Yanbiao Pan of Plano TX (US) for texas instruments incorporated, Jeffery Nilles of Los Altos CA (US) for texas instruments incorporated
IPC Code(s): H01L21/762, H01L27/06
Abstract: the present disclosure generally relates to shallow trench isolation (sti) processing with local oxidation of silicon (locos), and an integrated circuit formed thereby. in an example, an integrated circuit includes a semiconductor layer, a locos layer, an sti structure, and a passive circuit component. the semiconductor layer is over a substrate. the locos layer is over the semiconductor layer. the sti structure extends into the semiconductor layer. the passive circuit component is over and touches the locos layer.
Inventor(s): Jeffrey Alan West of Dallas TX (US) for texas instruments incorporated, Elizabeth Costner Stewart of Dallas TX (US) for texas instruments incorporated, Thomas Dyer Bonifield of Dallas TX (US) for texas instruments incorporated, Byron Lovell Williams of Plano TX (US) for texas instruments incorporated, Kashyap Barot of Bangalore (IN) for texas instruments incorporated, Viresh Chinchansure of Bangalore (IN) for texas instruments incorporated, Sreeram N S of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H01L21/768, H01L23/522, H01L23/528
Abstract: a microelectronic device including a galvanic isolator with filler metal within an upper isolation element. the galvanic isolator includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. the upper isolation element contains tines of filler metal which are electrically tied to each other and are electrically tied to the upper isolation element. the ends of the tines are rounded to minimize electric fields. the filler metal increases the overall metal density on the metal layer of the upper isolation element to meet the typical metal density requirements of modern microelectronic fabrication processing.
Inventor(s): Guangxu Li of Allen TX (US) for texas instruments incorporated, Yiqi Tang of Allen TX (US) for texas instruments incorporated, Rajen Manicon Murugan of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H01L23/498, H01L21/48, H01L23/00
Abstract: a semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. the top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. and integrated circuit (ic) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. an electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. at least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.
Inventor(s): Jeffrey Alan West of Dallas TX (US) for texas instruments incorporated, Thomas Dyer Bonifield of Dallas TX (US) for texas instruments incorporated, Toshiyuki Tamura of Ushiku-shi (JP) for texas instruments incorporated, Yoshihiro Takei of Kashiwa-shi (JP) for texas instruments incorporated
IPC Code(s): H01L23/58, H01L21/762, H01L23/00, H01L23/532, H01L23/544
Abstract: a microelectronic device including an isolation device. the isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. the inorganic dielectric plateau contains an upper etch stop layer and a lower etch stop layer between the upper isolation element and the lower isolation element. the upper etch stop layer provides an end point signal during the plateau etch process which provides feedback on the amount of inorganic dielectric plateau which has been etched. the lower etch stop layer provides a traditional etch stop function to provide for a complete plateau etch and protection of an underlying metal bond pad. the inorganic dielectric plateau also contains alternating layers of high stress and low stress silicon dioxide, which provide a means of reinforcement of the inorganic dielectric plateau.
Inventor(s): Juan HERBSOMMER of Allen TX (US) for texas instruments incorporated, Yiqi TANG of Allen TX (US) for texas instruments incorporated, Rajen Manicon MURUGAN of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H01L23/66, H01Q1/22, H01Q13/02
Abstract: in some examples, a semiconductor package includes a semiconductor die; a conductive member coupled to the semiconductor die; and a multi-layer package substrate. the multi-layer package substrate includes a first horizontal metal layer to provide a ground connection; a second horizontal metal layer above the first horizontal metal layer; vertical members coupling to the first and second horizontal metal layers; and a mold compound covering the first and second horizontal metal layers and the vertical members. the first horizontal metal layer, the second horizontal metal layer, and the vertical members together form a structure including a conductive strip coupled to the conductive member, a transition member coupled to the conductive strip, a waveguide coupled to the transition member, and a horn antenna coupled to the waveguide.
Inventor(s): Udit RAWAT of West Lafayette IN (US) for texas instruments incorporated, Bichoy BAHR of Allen TX (US) for texas instruments incorporated, Swaminathan SANKARAN of Allen TX (US) for texas instruments incorporated, Baher S. HAROUN of Allen TX (US) for texas instruments incorporated
IPC Code(s): H01L23/00, A61B8/00
Abstract: in examples, a semiconductor die comprises a semiconductor substrate having a surface, the surface having first and second surface portions, and a radiator layer on the surface. the radiator layer comprises a metal member having a first metal member portion above the first surface portion and a second metal member portion above the second surface portion, a first distance between the first metal member portion and the first surface portion, and a second distance between the second metal member portion and the second surface portion, the first distance less than the second distance. the radiator layer includes first and second electrodes. the radiator layer includes a piezoelectric layer extending along a length of the radiator layer and on each of the first and second electrodes, the piezoelectric layer between the first and second metal members and the semiconductor substrate.
20240113065.DOUBLE STITCH WIREBONDS_simplified_abstract_(texas instruments incorporated)
Inventor(s): Xiaolin KANG of Chengdu (CN) for texas instruments incorporated, Ziqi WANG of Chengdu (CN) for texas instruments incorporated, Huoyun DUAN of Chengdu (CN) for texas instruments incorporated, Peng PENG of Chengdu (CN) for texas instruments incorporated, Ye ZHUANG of Chengdu (CN) for texas instruments incorporated, Xiaoling KANG of Chengdu (CN) for texas instruments incorporated, Hongxia DENG of Chengdu (CN) for texas instruments incorporated
IPC Code(s): H01L23/00
Abstract: in some examples, a semiconductor package comprises an electrically conductive surface and a bond wire coupled to the electrically conductive surface. the bond wire includes a first stitch bond coupled to the electrically conductive surface, and a second stitch bond contiguous with the first stitch bond and coupled to the electrically conductive surface. the second stitch bond is partially, but not completely, overlapping with the first stitch bond.
20240113094.GALVANIC ISOLATION DEVICE_simplified_abstract_(texas instruments incorporated)
Inventor(s): Jeffrey Alan West of Plano TX (US) for texas instruments incorporated, Sreeram N. S. of Bangalore (IN) for texas instruments incorporated, Kashyap Barot of Bangalore (IN) for texas instruments incorporated, Thomas Dyer Bonifield of Dallas TX (US) for texas instruments incorporated, Byron Lovell Williams of Plano TX (US) for texas instruments incorporated, Elizabeth Costner Stewart of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H01L25/18, H01F27/28, H01F27/29, H01F27/32, H01L23/00, H01L27/01
Abstract: a microelectronic device includes a galvanic isolation device on a silicon substrate and a semiconductor device on a semiconductor substrate. the galvanic isolation device includes a lower isolation element over the silicon substrate and an upper isolation element above the lower isolation element, separated by a dielectric plateau that comprises inorganic dielectric material extending from the lower isolation element to the upper isolation element. the galvanic isolation device includes lower bond pads connected to the lower isolation element adjacent to the dielectric plateau, and upper bond pads over the dielectric plateau, connected to the upper isolation element. the semiconductor device includes an active component, and device bond pads coupled to the active component. the microelectronic device includes first electrical connections to the lower bond pads and second electrical connections to the upper bond pads. the first electrical connections or the second electrical connections are connected to the device bond pads.
Inventor(s): Yoshihiro Takei of USHIKU (JP) for texas instruments incorporated, Mitsuhiro Sugimoto of TSUKUBA (JP) for texas instruments incorporated, Byron Lovell Williams of Plano TX (US) for texas instruments incorporated, Jeffrey Alan West of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H01L27/01, H01L21/02, H01L23/00, H01L23/31
Abstract: a microelectronic device including an isolation device with a stabilized dielectric. the isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. the dielectric sidewall of the inorganic dielectric plateau is stabilized in a nitrogen containing plasma which forms a sionsurface on the dielectric sidewall of the inorganic dielectric plateau. the sionsurface on the dielectric sidewall of the inorganic dielectric plateau reduces ingress of moisture into the dielectric stack of the inorganic dielectric plateau.
Inventor(s): Jeffrey Alan West of Dallas TX (US) for texas instruments incorporated, Yoshihiro Takei of USHIKU (JP) for texas instruments incorporated, Mitsuhiro Sugimoto of TSUKUBA (JP) for texas instruments incorporated
IPC Code(s): H01L27/01
Abstract: a microelectronic device includes a lower isolation element and an upper isolation element, separated by an isolation dielectric layer stack. the microelectronic device includes a lower field reduction layer over the lower isolation element, under the isolation dielectric layer stack. the lower field reduction layer includes a first dielectric layer adjacent to the isolation dielectric layer stack, and a second dielectric layer over the first dielectric layer. a dielectric constant of the first dielectric layer is greater than a dielectric constant of the second dielectric layer. the dielectric constant of the second dielectric layer is greater than a dielectric constant of the isolation dielectric layer stack adjacent to the lower field reduction layer. methods of forming example microelectronic device having lower field reduction layers are disclosed.
Inventor(s): Sreeram Nasum Subramanyam of Bangalore (IN) for texas instruments incorporated, Shraddha Balasaheb Keripale of Kolhapur (IN) for texas instruments incorporated, Chinna Veerappan Venkatachalam of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H01L27/02, H01L23/00, H01L25/065
Abstract: examples of low capacitance bidirectional and unidirectional electrostatic discharge (esd) protection devices for high voltage (e.g., 15 kv, 30 kv) applications are provided. such devices include a circuit of a diode and a zener diode coupled via their anodes to form an npn structure and another, low capacitance diode coupled in series with the npn structure. such circuit may be configured on each of two dies, and the circuits coupled via wire bonds. additional wire bonds may be used to respectively couple two pins of the device to the two circuits, or the pins may be coupled to the circuits via respective conductive die attaches. in a multichip module (mcm) topology, the npn diode structure may be coupled to two low capacitance diodes on one die, and that circuit may be coupled to a third low capacitance diode disposed on another die. some arrangements employ an insulator in conjunction with a single die. some arrangements enable flipchip fabrication technology.
20240113102.BURIED TRENCH CAPACITOR_simplified_abstract_(texas instruments incorporated)
Inventor(s): Umamaheswari Aghoram of Richardson TX (US) for texas instruments incorporated, Guruvayurappan Mathur of Allen TX (US) for texas instruments incorporated, Robert Oppen of Phoenix AZ (US) for texas instruments incorporated, Tawen Mei of Sunnyvale CA (US) for texas instruments incorporated
IPC Code(s): H01L27/06, H01L29/66, H01L29/94
Abstract: a microelectronic device includes a buried trench capacitor below an electronic component of the microelectronic device. in one embodiment, the buried trench capacitor may be formed between a silicon oxide capped p-type buried trench capacitor polysilicon region and a buried trench capacitor deep n-type region separated by buried trench capacitor liner dielectric. in a second embodiment, the buried trench capacitor may be formed by a buried trench capacitor polysilicon region and a p-type silicon epitaxial region separated by a buried trench capacitor liner dielectric. one terminal of the deep trench capacitor is made through the substrate via a deep trench substrate contact. the second terminal of the deep trench capacitor is made via a well contact that connects to the capacitor through a deep well region in one embodiment and through a polysilicon layer in a second embodiment.
Inventor(s): Jeffrey Alan West of Dallas TX (US) for texas instruments incorporated, Hung-Yu Chou of Taipei city (TW) for texas instruments incorporated, Byron Lovell Williams of Plano TX (US) for texas instruments incorporated, Thomas Dyer Bonifield of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H01L23/00, H01L21/56, H01L23/31, H01L25/16
Abstract: a microelectronic device includes a galvanic isolation component having a lower isolation element over a substrate with lower bond pads connected to the lower isolation element, a dielectric plateau over the lower isolation element that does not extend to the lower bond pads, and an upper isolation element and upper bond pads over the dielectric plateau. the upper bond pads are laterally separated from the lower bond pads by an isolation distance. the microelectronic device includes high voltage wire bonds on the upper bond pads that extend upward, within 10 degrees of vertical, for a vertical distance greater than the isolation distance. the microelectronic device further includes low voltage wire bonds on the lower bond pads that have a loop height directly over a perimeter of the substrate that is less than 5 times a wire diameter of the low voltage wire bonds.
Inventor(s): Scott William JESSEN of Allen TX (US) for texas instruments incorporated, Steven Lee PRINS of Fairview TX (US) for texas instruments incorporated, Sameer Prakash PENDHARKAR of Allen TX (US) for texas instruments incorporated, Abbas ALI of Plano TX (US) for texas instruments incorporated, Gregory Boyd SHINN of Dallas TX (US) for texas instruments incorporated
IPC Code(s): H01L49/02, H01L27/06
Abstract: a passive circuit component includes an edge having a low line edge roughness (ler). a method for manufacturing the passive circuit component includes a self-aligned double patterning (sadp) etch process using a tri-layer process flow. the tri-layer process flow includes use of an underlayer, hard mask, and photoresist. the passive circuit component made by this method achieves improved mismatch between like components due to the low ler.
20240113217.TRENCH SHIELDED TRANSISTOR_simplified_abstract_(texas instruments incorporated)
Inventor(s): Hong Yang of Wylie TX (US) for texas instruments incorporated, Thomas Grebs of Bethlehem PA (US) for texas instruments incorporated, Yunlong Liu of Chengdu (CN) for texas instruments incorporated, Sunglyong Kim of Allen TX (US) for texas instruments incorporated, Lindong Li of Chengdu (SC) for texas instruments incorporated, Peng Li of Chongqing (CN) for texas instruments incorporated, Seetharaman Sridhar of Richardson TX (US) for texas instruments incorporated, Yeguang Zhang of Chengdu (SC) for texas instruments incorporated, Sheng pin Yang of Chengdu (SC) for texas instruments incorporated
IPC Code(s): H01L29/78, H01L21/8234, H01L27/092, H01L29/423
Abstract: an integrated circuit includes first and second trenches in a semiconductor substrate and a semiconductor mesa between the first and second trenches. a source region having a first conductivity type and a body region having an opposite second conductivity type are located within the semiconductor mesa. a trench shield is located within the first trench, and a gate electrode is over the trench shield between first and second sidewalls of the first trench. a gate dielectric is on a sidewall of the first trench between the gate electrode and the body region, and a pre-metal dielectric (pmd) layer is over the gate electrode. a gate contact through the pmd layer touches the gate electrode between the first and second sidewalls, and a trench shield contact through the pmd layer touches the trench shield between the first and second sidewalls.
Inventor(s): Yiqi Tang of Allen TX (US) for texas instruments incorporated, Rajen Manicon Murugan of Dallas TX (US) for texas instruments incorporated, Juan Alejandro Herbsommer of Allen TX (US) for texas instruments incorporated
IPC Code(s): H01Q1/22, H01L23/31, H01L23/66, H05K1/02
Abstract: a described example includes an antenna formed in a first conductor layer on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers, the multilayer package substrate having a board side surface opposite the device side surface; and a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the antenna.
Inventor(s): Sahana Sriraj of Dallas TX (US) for texas instruments incorporated, Ralph Braxton Wade, III of McKinney TX (US) for texas instruments incorporated
IPC Code(s): H02H9/02, H03K17/687
Abstract: a current limiter includes a gain adjustment circuit designed to change the response time (e.g., operation mode) of the current limiter. the current limiter may be designed to operate at different selectable speed modes (e.g., slow mode, fast mode) that affect how quickly the current limiter responds to an overcurrent stimulus. the speed modes may be selected by choosing between different current mirror arrangements in the gain adjustment circuit. regardless of which mode of operation is selected for the current limiter, a speedup circuit may also be implemented, which includes a switch to initiate a nonlinear speedup of the response time after a certain overcurrent stimulus is received.
20240113611.SLEW-RATE CONTROL FOR POWER STAGES_simplified_abstract_(texas instruments incorporated)
Inventor(s): Maik Peter KAUFMANN of FREISING (DE) for texas instruments incorporated, Stefan HERZER of MARZLING (DE) for texas instruments incorporated, Michael LUEDERS of FREISING (DE) for texas instruments incorporated
IPC Code(s): H02M1/00, H02M3/158, H03K17/16
Abstract: a circuit includes a half-bridge circuit is configured to provide a switching voltage responsive to respective high-side and low-side drive signals. high-side slew control circuitry is configured to provide a high-side slew-compensated control signal responsive to a high-side enable signal and a slew current signal representative of a slew rate at a switching output. a high-side driver is configured to provide the high-side drive signal responsive to the high-side slew-compensated control signal. low-side slew control circuitry is configured to provide a low-side slew-compensated drive signal responsive to a low-side enable signal and the slew current signal. a low-side driver is configured to provide the low-side drive signal responsive to the low-side slew-compensated control signal. a capacitor is coupled between the high-side and low-side slew control circuitry and is configured to convert the slew rate to the slew current signal.
Inventor(s): Indumini W Ranmuthu of Plano TX (US) for texas instruments incorporated, Michael T Direnzo of Coppell TX (US) for texas instruments incorporated
IPC Code(s): H02M3/158, H02M1/08
Abstract: a voltage regulator control circuit includes a transistor input controller. the transistor input controller forces a slew control signal on its slew control output to a state responsive to a change in a load condition and forces an on signal to a state on its first transistor control output. a first transistor has a first control input and first and second current terminals. a second transistor couples to the first transistor. a driver has a slew control input, a driver input, and a driver output. the driver input couples to the first transistor control output. the driver output couples to the first control input. responsive to a first logic state of the slew control signal and a first state of the on signal, the driver provides a higher current to the first control input, and responsive to a second state of the slew control signal and a first state of the on signal, the driver provides a lower current to the first control input.
Inventor(s): Jian Liang of Shanghai (CN) for texas instruments incorporated, Chen Feng of Shanghai (CN) for texas instruments incorporated, Zichen Feng of Shanghai (CN) for texas instruments incorporated
IPC Code(s): H02M3/158, H02M1/00
Abstract: a boost converter that provides a wide average current limiting range includes a switch coupled to an inductor output and a power input, a diode coupled to the inductor output and an output terminal load and configured to conduct current in only one direction away from the inductor output and toward the output terminal, a clamp circuit coupled to the diode and the switch, and a minimum time off module coupled to the diode and the switch. the clamp circuit is configured to clamp an inductor output current to a reference current while the converter is operating in a continuous conduction mode (ccm) of operation. the minimum time off module is configured to cause the inductor output current to be zero for at least a time twhile the converter is operating in a pulse frequency modulation (pfm) mode of operation.
Inventor(s): Bikash Kumar PRADHAN of Bengaluru (IN) for texas instruments incorporated, Preetam Charan Anand TADEPARTHY of Bengaluru (IN) for texas instruments incorporated, Muthusubramanian VENKATESWARAN of Bengaluru (IN) for texas instruments incorporated, Venkatesh WADEYAR of Bengaluru (IN) for texas instruments incorporated, Siddaram MATHAPATHI of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): H02M3/158, H02M1/00
Abstract: a controller includes: a pulse-width modulation (pwm) circuit; a control loop; and a reference voltage controller. the control loop has: a feedback input adapted to be coupled to an output voltage of a power stage; a control loop output coupled to a pwm control input; and an operational amplifier with a first feedback input, a first reference input, and an amplifier output, the first feedback input connected to the feedback input, and the amplifier output coupled to the pwm control input. the reference voltage controller has a reference voltage output coupled to the first reference input, the reference voltage controller configured to adjust a reference voltage provided to the reference voltage output responsive to a dynamic error estimate based on error in the operational amplifier.
20240113624.MULTI-PHASE BUCK-BOOST CONVERTER_simplified_abstract_(texas instruments incorporated)
Inventor(s): Eric SOUTHARD of Richardson TX (US) for texas instruments incorporated, Daniel A. MAVENCAMP of Dallas TX (US) for texas instruments incorporated, Qiong LI of Allen TX (US) for texas instruments incorporated, Shishuo ZHAO of Richardson TX (US) for texas instruments incorporated
IPC Code(s): H02M3/158, H02M1/00, H02M1/08
Abstract: a multi-phase buck-boost converter includes a first half-bridge circuit, a second half-bridge circuit, a third half-bridge circuit, and a control circuit. the first half-bridge circuit is coupled to a first inductor terminal. the second half-bridge circuit is coupled to a second inductor terminal. the third half-bridge circuit is coupled to a third inductor terminal, a system voltage terminal, and a battery terminal. the control circuit is coupled to the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit. the control circuit is configured to transition the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operation in a buck mode to operation in a buck-boost mode based on an off-time of the first half-bridge being less than a particular time.
Inventor(s): Shagun Dusad of Bangalore (IN) for texas instruments incorporated, Vysakh Karthikeyan of Kerala (IN) for texas instruments incorporated, Naveen Mahadev of Bangalore (IN) for texas instruments incorporated, Rafi Mahammad of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03H7/42, H01F27/28, H03H7/00
Abstract: a balun includes a first winding which has a first terminal coupled to an input, and a second terminal coupled to a reference potential terminal. the balun includes a second winding magnetically coupled to the first winding. the second winding has a first terminal coupled to a first differential output, a second terminal coupled to a second differential output, and a tap coupled to the reference potential terminal. the balun includes a first capacitor which has a first terminal coupled to the first winding and a second terminal coupled to the second winding. the balun includes a third winding which has a first terminal coupled to the reference potential terminal and a floating second terminal. the balun includes a second capacitor which has a first terminal coupled to the third winding and a second terminal coupled to the second winding.
Inventor(s): Nithin Sathisan Poduval of Sunnyvale CA (US) for texas instruments incorporated, Abishek Manian of San Jose CA (US) for texas instruments incorporated, Roland Nii Ofei Ribeiro of San Jose CA (US) for texas instruments incorporated
IPC Code(s): H03K19/0185, H03K3/037
Abstract: an example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.
Inventor(s): Yogesh DARWHEKAR of Bangalore (IN) for texas instruments incorporated, Abhrarup BARMAN ROY of Bangalore (IN) for texas instruments incorporated, Subhashish MUKHERJEE of Bangalore (IN) for texas instruments incorporated, Peeyoosh MIRAJKAR of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03K21/08, H03K17/687
Abstract: in an example, a system includes an n divider coupled to an output of a low dropout regulator. the system also includes a load balancing circuit coupled to the n divider and configured to sink a load balancing current at the output of the low dropout regulator during one or more phases of the n divider. the system includes a switch coupled to the load balancing circuit and configured to connect the load balancing circuit to the output of the low dropout regulator during the one or more phases of the n divider.
Inventor(s): BICHOY BAHR of ALLEN TX (US) for texas instruments incorporated, YOGESH RAMADASS of SAN JOSE CA (US) for texas instruments incorporated
IPC Code(s): H03L7/099, H03B5/32, H03H9/02, H03K3/0231, H03L7/085, H03M1/46
Abstract: a clock circuit includes a voltage-controlled oscillator (vco) having a control input and a first clock output. the clock circuit includes a frequency-locked loop (fll) having an fll input and a control output, the control output coupled to the control input. a microelectromechanical system (mems) resonator-based oscillator has a second clock output. a multiplexer has a first multiplexer input, a second multiplexer input, a selection input, and a multiplexer output. the first multiplexer input is coupled to the first clock output. the second multiplexer input is coupled to the second clock output. the multiplexer output is coupled to the fll input.
Inventor(s): Jayawardan Janardhanan of Bangalore (IN) for texas instruments incorporated, Yogesh Darwhekar of Bangalore (IN) for texas instruments incorporated, Subhashish Mukherjee of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H03M1/10
Abstract: a system includes a first digital-to-time converter (dtc) adapted to receive a first dtc code and a first clock signal. the first dtc provides an output clock signal. the system includes a calibration dtc adapted to receive a calibration dtc code and a second clock signal. the calibration dtc provides a calibration output signal. the system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. the system includes an average computation module which provides an average value of the outputs of the latch comparator. the system includes a digital controller adapted to receive the average value. the digital controller provides the dtc code and the calibration dtc code.
Inventor(s): Debapriya SAHU of Bengaluru (IN) for texas instruments incorporated, Pranav SINHA of Bengaluru (IN) for texas instruments incorporated, Meghna AGRAWAL of Bengaluru (IN) for texas instruments incorporated
IPC Code(s): H03M1/46, H03M1/06, H03M1/18
Abstract: an analog-to-digital converter (adc) includes a switched capacitor circuit, a comparator, and a control circuit. the switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. the comparator has an input coupled to the output of the switched capacitor circuit and has an output. the control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the adc prior to the sample acquisition cycle.
Inventor(s): Tolga DINC of Dallas TX (US) for texas instruments incorporated, Swaminathan SANKARAN of Allen TX (US) for texas instruments incorporated
IPC Code(s): H04B1/18, H03H2/00, H04B1/00
Abstract: in examples, an electronic device includes an antenna and a transmitter line. the transmitter line includes a double-tuned transformer having first and second windings, the first winding having first and second ends, the second winding having third and fourth ends, and the third end coupled to the antenna. the transmitter line includes a first capacitor coupled between the first and second ends. the transmitter line also includes a second capacitor coupled between the third and fourth ends, and a switch coupled between the first end and a reference terminal.
Inventor(s): June Chul Roh of Allen TX (US) for texas instruments incorporated, Pierre Bertrand of Antibes (FR) for texas instruments incorporated
IPC Code(s): H04L1/00, H03M13/00, H03M13/09, H03M13/15, H03M13/25, H03M13/27, H03M13/29, H04L1/1812, H04L27/26
Abstract: a method for performing code block segmentation for wireless transmission using concatenated forward error correction encoding includes receiving a transport block of data for transmission having a transport block size, along with one or more parameters that define a target code rate. a number n of inner code blocks needed to transmit the transport block is determined. a number m—outer code blocks may be calculated based on the number of inner code blocks and on encoding parameters for the outer code blocks. the transport block may then be segmented and encoded according to the calculated encoding parameters.
Inventor(s): Ani Xavier of Bangalore (IN) for texas instruments incorporated, Jagannathan Venkataraman of Bangalore (IN) for texas instruments incorporated
IPC Code(s): H04L7/00
Abstract: an example system includes: interleaving circuitry including a data input, a plurality of data outputs, and a plurality of clock inputs, the data input coupled to the received data input and each of the plurality of clock inputs coupled to one of the plurality of receiver clock outputs; and handoff circuitry coupled to the interleaving circuitry, the handoff circuitry including: comparison circuitry coupled to the clock generation circuitry and configured to compare the plurality of receiver clocks to the transmission clock; clock configuration circuitry coupled to the comparison circuitry and configured to select one of the plurality of receiver clocks based on the comparison circuitry; and a plurality of flip-flops coupled to the clock configuration circuitry and configured to convert the plurality of data outputs from the plurality of receiver clocks to the transmission clock to generate a plurality of transmission data streams based on the one of the plurality of receiver clocks selected by the clock configuration circuitry.
20240114174.PREVENTION OF START CODE CONFUSION_simplified_abstract_(texas instruments incorporated)
Inventor(s): Vivienne Sze of Dallas TX (US) for texas instruments incorporated, Madhukar Budagavi of Plano TX (US) for texas instruments incorporated, Akira Osamoto of Plano TX (US) for texas instruments incorporated, Yasutomo Matsuba of Allen TX (US) for texas instruments incorporated
IPC Code(s): H04N19/70
Abstract: a method and a video processor for preventing start code confusion. the method includes aligning bytes of a slice header relating to slice data when the slice header is not byte aligned or inserting differential data at the end of the slice header before the slice data when the slice header is byte aligned, performing emulation prevention byte insertion on the slice header, and combine the slice header and the slice data after performing emulation prevention byte insertion.
Inventor(s): Woo-Shik Kim of San Diego CA (US) for texas instruments incorporated, Do-Kyoung Kwon of Allen TX (US) for texas instruments incorporated, Minhua Zhou of San Diego CA (US) for texas instruments incorporated
IPC Code(s): H04N19/86, H04N19/117, H04N19/186, H04N19/463, H04N19/70, H04N19/80, H04N19/82, H04N19/91
Abstract: techniques for signaling of sample adaptive offset (sao) information that may reduce the coding rate for signaling such information in the compressed bit stream are provided. more specifically, techniques are provided that allow sao information common to two or more of the color components to be signaled using one or more syntax elements (flags or indicators) representative of the common information. these techniques reduce the need to signal sao information separately for each color component.
Inventor(s): Yuval MATAR of Kiryat Mozkin (IL) for texas instruments incorporated, Yaron ALPERT of Hod Hasharon (IL) for texas instruments incorporated
IPC Code(s): H04W74/06, H04L5/00, H04W74/08
Abstract: a device configured to communicate via a wi-fi channel obtains a contention-free access period on the wi-fi channel. the device sends a first probe packet to a receiving wi-fi device during the contention-free access period, with at least one parameter of a wi-fi transmitter of the wi-fi transceiver set to a first setting, and waits for a first reply period. the device sends a second probe packet to the receiving wi-fi device during the contention-free access period, with the at least one parameter of the wi-fi transmitter set to a second setting, where the second setting is based on a result of the first reply period, and waits for a second reply period. the device sets the at least one parameter of the wi-fi transmitter to a data packet setting, where the data packet setting is based at least on a result of the second reply period.
TEXAS INSTRUMENTS INCORPORATED patent applications on April 4th, 2024
- TEXAS INSTRUMENTS INCORPORATED
- B29C64/165
- B22F10/00
- B22F10/14
- B22F12/37
- B22F12/53
- B22F12/55
- B22F12/57
- B28B1/00
- B33Y10/00
- B33Y30/00
- B33Y70/00
- B33Y80/00
- H01L21/02
- H01L21/288
- H01L21/67
- Texas instruments incorporated
- G01R33/00
- G01R33/09
- G01R33/04
- F21V8/00
- G02B3/00
- G06F9/38
- G06F7/02
- H01F27/32
- H01F41/12
- H01F41/04
- H01F27/28
- H01F27/29
- H01L21/762
- H01L27/06
- H01L21/768
- H01L23/522
- H01L23/528
- H01L23/498
- H01L21/48
- H01L23/00
- H01L23/58
- H01L23/532
- H01L23/544
- H01L23/66
- H01Q1/22
- H01Q13/02
- A61B8/00
- H01L25/18
- H01L27/01
- H01L23/31
- H01L27/02
- H01L25/065
- H01L29/66
- H01L29/94
- H01L21/56
- H01L25/16
- H01L49/02
- H01L29/78
- H01L21/8234
- H01L27/092
- H01L29/423
- H05K1/02
- H02H9/02
- H03K17/687
- H02M1/00
- H02M3/158
- H03K17/16
- H02M1/08
- H03H7/42
- H03H7/00
- H03K19/0185
- H03K3/037
- H03K21/08
- H03L7/099
- H03B5/32
- H03H9/02
- H03K3/0231
- H03L7/085
- H03M1/46
- H03M1/10
- H03M1/06
- H03M1/18
- H04B1/18
- H03H2/00
- H04B1/00
- H04L1/00
- H03M13/00
- H03M13/09
- H03M13/15
- H03M13/25
- H03M13/27
- H03M13/29
- H04L1/1812
- H04L27/26
- H04L7/00
- H04N19/70
- H04N19/86
- H04N19/117
- H04N19/186
- H04N19/463
- H04N19/80
- H04N19/82
- H04N19/91
- H04W74/06
- H04L5/00
- H04W74/08
