TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on July 11th, 2024
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. on July 11th, 2024
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.: 63 patent applications
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. has applied for patents in the areas of H01L29/66 (16), H01L29/423 (11), H01L23/00 (11), H01L23/31 (10), H01L29/06 (9) H01L23/5226 (3), H01L25/18 (2), H01L27/0924 (2), G02B6/124 (1), H01L27/0255 (1)
With keywords such as: layer, structure, semiconductor, gate, portion, region, dielectric, device, die, and substrate in patent application abstracts.
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s): Tai-Chun HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Stefan RUSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/124, G02B6/12, G02B6/13, H01L27/144, H01L31/0232, H01L31/028, H01L31/105, H01L31/18
CPC Code(s): G02B6/124
Abstract: the present disclosure provides a semiconductor structure. the semiconductor structure includes a waveguide structure, a photoelectric material, and a transistor. the waveguide structure is disposed on a substrate and includes a first doping region having a first type of dopant and a second doping region having a second type of dopant different from the first type. the photoelectric material is disposed proximal to a junction of the first doping region and the second doping region. the transistor is disposed on the substrate at a level same as a level of the waveguide structure. a method of manufacturing the semiconductor structure is also provided.
Inventor(s): Chan-Hong Chern of Palo Alto CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02F1/025, G02B6/12, G02F1/21, G02F1/225
CPC Code(s): G02F1/025
Abstract: an optical phase-shifting device includes a ribbed waveguide portion on an insulating layer, the waveguide portion having a p-n or p-i-n junction extending in a longitudinal direction and having a height. a pair of slab portions are disposed adjacent the waveguide portion, one on each side of the ribbed waveguide portion and on the insulation layer. the slab portion have higher doping concentrations than the respective doping concentrations in the ribbed waveguide portion. at least a portion of each slab portion has a height increasing with distance from the waveguide portion, with the slab height being smaller than that of the waveguide portion at the junction between the waveguide portion and slab portion. a pair of contact portions are formed adjacent the respective slab portion and further away from the waveguide portion. a portion of each contact portion can also have a height varying with distance from the waveguide portion.
Inventor(s): Yung-Yao LEE of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, C09D1/00, C09D5/00, C23C14/06, C23C14/08, C23C16/34, C23C16/40
CPC Code(s): G03F7/70316
Abstract: a bottom lens for an immersion exposure tool includes a hydrophobic coating on the sidewalls of the bottom lens. a bottom portion of the bottom lens is not coated with the hydrophobic coating to maintain the optical performance of the bottom lens and to not distort a pattern that is to be transferred to a substrate. the hydrophobic coating may reduce the thermal instability of the bottom lens. this may reduce overlay variation during operation of the immersion exposure tool, which may increase manufacturing yield, decrease device failures, and/or decrease rework and repairs.
Inventor(s): Po-Ming SHIH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hung LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00
CPC Code(s): G03F7/705
Abstract: a photolithography system utilizes tin droplets to generate extreme ultraviolet radiation for photolithography. the photolithography system irradiates the droplets with a laser. the droplets become energized and emit extreme ultraviolet radiation. a collector reflects the extreme ultraviolet radiation toward a photolithography target. the photolithography system reduces splashback of the tin droplets onto the receiver by generating a net electric charge within the droplets using a charge electrode and decelerating the droplets by applying an electric field with a counter electrode.
Inventor(s): Feng-Wei KUO of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Shiang LIAO of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, G02B6/122, G02B6/124, G02B27/00, G05B19/18, G06F30/39, G06F30/394, G06F30/398
CPC Code(s): G06F30/392
Abstract: a method and system for generating a physical layout for a grating coupler integrated in a photonically-enabled circuit are disclosed herein. in some embodiments, the method receives a parametrized wavelength, a parametrized first refractive index, a parametrized second refractive index, a parametrized taper length, a parametrized width, a parametrized grating length, and a parametrized incident angle of the optical beam incident onto the grating coupler and generates a physical layout for the grating coupler based on the received parametrized inputs, the generating of the physical layout is according to a predefined model, and outputs the physical layout of the grating coupler for manufacturing under a semiconductor fabrication process.
Inventor(s): Jui-Jen WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Win-San KHWA of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Chieh LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Fan CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/06, G11C7/08
CPC Code(s): G11C7/065
Abstract: a circuit includes first and second data lines, a sense amplifier including first and second input terminals, a first p-type metal-oxide-semiconductor (pmos) transistor coupled in series with a first capacitive device between the first data line and the second input terminal, a second pmos transistor coupled in series with a second capacitive device between the second data line and the first input terminal, a third pmos transistor coupled between the first data line and the first input terminal, a fourth pmos transistor coupled between the second data line and the second input terminal, a first n-type metal-oxide-semiconductor (nmos) transistor configured to selectively couple each of the first pmos transistor and the first capacitive device to a ground node, and a second nmos transistor configured to selectively couple each of the second pmos transistor and the second capacitive device to the ground node.
20240233785. MEMORY REFRESH_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Hiroki Noguchi of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/10, G06F11/10, G11C7/06
CPC Code(s): G11C7/1051
Abstract: performing refresh operation in a memory device is provided. a refresh operation without address rotation is performed in a cell array of the memory device. performing the refresh operation without address rotation is repeated for a predetermined number of times. after repeating performing the refresh operation with address rotation for the predetermined number of times, a refresh operation with address rotation is performed in the cell array.
Inventor(s): Je-Min Hung of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Win-San Khwa of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Fan Chang of Taichung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C7/22, G06F7/544, G11C7/10, G11C7/12, G11C7/14, G11C7/16
CPC Code(s): G11C7/222
Abstract: an input/output (i/o) circuit for a memory device is provided. the i/o circuit includes a charge integration circuit coupled to a bitline of the memory device. the charge integration circuit provides a sensing voltage based on a decrease of a voltage on the bitline. a comparator is coupled to the charge integration circuit. the comparator compares the sensing voltage with a reference voltage and provides an output voltage based on the comparison. a time-to-digital converter coupled to the comparator. the time to digital convertor converts a time associated with the output voltage to a digital value.
Inventor(s): Huan-Sheng WEI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzer-Min SHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Zhiqiang WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/22, H10B51/30, H10B51/40
CPC Code(s): G11C11/2275
Abstract: a memory circuit includes a plurality of memory cells, each memory cell of the plurality of memory cells including a gate electrode, a ferroelectric layer adjacent to the gate electrode, a channel layer adjacent to the ferroelectric layer, the channel layer including indium gallium zinc oxide (igzo), and source and drain contacts adjacent to the channel layer opposite the ferroelectric layer. the memory circuit is configured to, during write operations to a memory cell of the plurality of memory cells, apply a plurality of voltage levels to the gate electrode relative to a ground voltage level applied to the source and drain contacts, a first voltage level of the plurality of voltage levels has a positive polarity and a first magnitude, and a second voltage level of the plurality of voltage levels has a negative polarity and a second magnitude greater than the first magnitude.
20240233820. RRAM CIRCUIT_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Chung-Cheng CHOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Zheng-Jun LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Ling TSENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C13/00
CPC Code(s): G11C13/0038
Abstract: a resistive random-access memory (rram) circuit includes a current source configured to output a first current, a first n-type transistor including a first drain terminal configured to receive the first current, an rram device, second and third n-type transistors including respective second and third drain terminals coupled to an output terminal of the rram device, an amplifier including a non-inverting input coupled to the first drain terminal, an inverting input configured to receive a first reference voltage level, and an output coupled to a gate of each of the first through third n-type transistors, a fourth n-type transistor coupled between the second n-type transistor and a power supply reference node, and a comparator including a non-inverting input configured to receive a second reference voltage level, an inverting input coupled to each of the second and third drain terminals, and an output coupled to a gate of the fourth n-type transistor.
Inventor(s): Chin-Ta CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hua-Tai LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Han-Wei WU of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Yuan HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/027, H01L21/3213
CPC Code(s): H01L21/0274
Abstract: in a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.
Inventor(s): Chien-Chun Hu of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Chyi-Tsong Ni of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Wei Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, B05D3/06, H01L21/02
CPC Code(s): H01L21/67115
Abstract: an ultraviolet (uv) lamp assembly of a uv curing tool is provided for curing a low dielectric constant (low-k) material layer of a semiconductor wafer. the uv lamp assembly includes: a uv lamp which emits uv light; a first reflector arranged proximate to a first side of the uv lamp, the first reflector including a first surface facing the uv lamp from which uv light emitted by the uv lamp is at least partially reflected; and a uv reflective coating partially coating the first surface of the reflector. suitably, a plurality of areas of the first surface of the reflector remain uncoated with the uv reflective coating and the plurality of uncoated areas are arranged to promote a uniform exposure of the semiconductor wafer to uv irradiation.
Inventor(s): Cheng-Shiuan Wong of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Wei Chiu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yu Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chiang Tsao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Jan Pei of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Jen Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/683
CPC Code(s): H01L21/6836
Abstract: a method includes attaching a carrier to a semiconductor wafer using a release film; removing the carrier from the semiconductor wafer; and performing a treatment process to remove the release film from the semiconductor wafer, the treatment process comprising: flowing an etchant through a diffusion plate within a treatment chamber, the diffusion plate comprising concentric rings separated by dividers, the concentric rings comprising a first concentric ring of holes, a second concentric ring of holes, and a third concentric ring of holes, each of the concentric rings having a different hole density; and performing a cleaning process on the semiconductor wafer.
Inventor(s): Yu-Chen CHEN of Hemei Township (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Fam SHIU of Toufen City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Lung WU of Zhunan Township (TW) for taiwan semiconductor manufacturing company, ltd., Yang-Ann CHU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jiun-Rong PAI of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/687, H01L21/67
CPC Code(s): H01L21/68742
Abstract: a wafer lift pin system is capable of dynamically modulating or adjusting the flow of gas into and out of lift pins of the wafer lift pin system to achieve and maintain a consistent pressure in supply lines that supply the gas to the lift pins. this enables the wafer lift pin system to precisely control the speed, acceleration, and deceleration of the lift pins to achieve consistent and repeatable lift pin rise times and fall times. a controller and various sensors and valves may control the gas pressures in the wafer lift pin system based on various factors, such as historic rise times, historic fall times, and/or the condition of the lift pins. this enables smoother and more controlled automatic operation of the lift pins, which reduces and/or minimizes wafer shifting and wafer instability, which may reduce processing defects and maintain or improve processing yields.
Inventor(s): Ting-Ya LO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Kuan LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., GARY LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Zi-Yi YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Wei YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jing-Ting SU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Lin TENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yen HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao-Kang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522
CPC Code(s): H01L21/76831
Abstract: a method for manufacturing a semiconductor device includes: preparing a conductive structure that includes a plurality of conductive features, adjacent two of which are spaced apart from each other by a corresponding one of a plurality of recesses;
Inventor(s): Ting-Ya LO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Kuan LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., GARY LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Zi-Yi YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Wei YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jing-Ting SU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Lin TENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yen HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao-Kang CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522
CPC Code(s): H01L21/76831
Abstract: conformally forming a dielectric capping layer on the conductive structure; forming a dielectric cover layer on the dielectric capping layer to fill the recesses; and removing a portion of the dielectric cover layer and a portion of the dielectric capping layer to expose the conductive features, so as to form a plurality of spacer features respectively filled in the recesses; wherein each of the dielectric capping layer and the dielectric cover layer is made of a dielectric material doped with metal oxide.
Inventor(s): Jen-Chun Liao of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Hung Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Yueh Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Lin of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kung-Chen Yeh of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/822, H01L21/3065, H01L21/56, H01L23/00, H01L23/31, H01L25/065
CPC Code(s): H01L21/822
Abstract: an integrated circuit package including integrated circuit dies and a method of forming are provided. the integrated circuit package may include a first integrated circuit die and a second integrated circuit die bonded to the first integrated circuit die. the first integrated circuit die may include a first substrate, a first interconnect structure, and a first bonding layer. the first interconnect structure may be between the first bonding layer and the first substrate. the second integrated circuit die may include a second substrate, a second interconnect structure, and a second bonding layer. the second interconnect structure may be between the second bonding layer and the second substrate. a first surface of the first bonding layer may be in direct contact with a first surface of the second bonding layer. a sidewall the first bonding layer and the first surface of the second bonding layer may form a first acute angle.
Inventor(s): Peng-Soon LIM of Johor (MY) for taiwan semiconductor manufacturing company, ltd., Zi-Wei FANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L27/088, H01L21/285, H01L29/66
CPC Code(s): H01L21/82345
Abstract: a semiconductor device includes a semiconductor substrate, a first gate structure over the substrate, a second gate structure over the substrate, first gate spacers, second gate spacers, first and second metal layers spanning over the first and second gate structures, first and second contact plugs extending through the first and second metal layers, respectively. the first gate structure includes a first gate dielectric, and a first work function metal layer over the first gate dielectric. the second gate structure is wider than the first gate structure, wherein the second gate structure includes a second gate dielectric, a second work function metal layer over the second gate dielectric, and a filling conductor over the second work function metal layer. the first contact plug is in contact with the first work function metal layer, and the second contact plug is in contact with the filling conductor.
Inventor(s): Chu-An LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hao WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Peng-Chung JANGJIAN of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Wen HSIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Teng-Chun TSAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Huang-Lin CHAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/3105, H01L21/762, H01L27/088, H01L29/06
CPC Code(s): H01L21/823481
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes an isolation feature formed over a substrate that includes a first fin and a second fin separated from each other by the isolation feature. the semiconductor device structure also includes an insulating fin structure formed in the isolation feature between the first fin and the second fin. the insulating fin structure includes a first insulating fin base partially formed within the isolation feature and a first insulating capping layer formed over a top surface of the first insulating fin base.
Inventor(s): Lung-Kun Chu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Mao-Lin Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Hao Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/3213, H01L27/092, H01L29/40, H01L29/423
CPC Code(s): H01L21/823842
Abstract: a semiconductor device includes a semiconductor substrate; a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate structure. the gate structure includes a gate dielectric layer disposed over the plurality of channel regions and a work function metal (wfm) structure disposed over the gate dielectric layer. the wfm structure includes an n-type wfm layer over the n-type channel region and not over the p-type channel region and further includes a p-type wfm layer over both the n-type wfm layer and the p-type channel region. the gate structure further includes a fill metal layer disposed over the wfm structure and in direct contact with the p-type wfm layer.
Inventor(s): Tsung-Shu Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wensen Hung of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yu Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/053, H01L21/52, H01L25/18
CPC Code(s): H01L23/053
Abstract: a manufacturing method of a semiconductor package includes the following steps. a package structure is provided over a substrate. a thermal interface layer is provided over the package structure. a lid structure is provided over the substrate, wherein the lid structure comprises a main body in contact with the package structure through the thermal interface layer and surrounding the package structure and a plurality of rib portions protruded from the main body and extended toward the package structure.
Inventor(s): Chih-Hao Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Fu Kao of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Hui Cheng of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Wei Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chien Pan of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/42, H01L21/56, H01L23/00, H01L23/31, H01L23/498, H01L23/538, H01L25/065, H01L27/06
CPC Code(s): H01L23/42
Abstract: provided are a package structure and a method of forming the same. the package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (tim), and an adhesive pattern. the first die and the second die group are disposed side by side on the interposer. the underfill layer is disposed between the first die and the second die group. the adhesive pattern at least overlay the underfill layer between the first die and the second die group. the tim has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. the adhesive pattern separates the underfill layer from the tim.
Inventor(s): Tzuan-Horng Liu of Longtan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L21/48, H01L23/31, H01L23/538, H01L25/00, H01L25/10
CPC Code(s): H01L23/49816
Abstract: a method includes forming a reconstructed wafer including forming an under-bump metallurgy (ubm) over a first carrier, forming a first interconnect structure including a plurality of redistribution lines over and electrically connecting to the ubm, bonding a first die over the first interconnect structure, encapsulating the first die in a first encapsulant, forming a second interconnect structure over the first die, and bonding a second die over the second interconnect structure. the method further includes de-bonding the reconstructed wafer from the first carrier, forming an electrical connector physically contacting the ubm, sawing the reconstructed wafer to form a plurality of packages, and bonding one of the plurality of packages to a package component.
Inventor(s): Po-Han Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jui Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsiang Hu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/56, H01L21/66, H01L21/683, H01L21/768, H01L21/78, H01L23/00, H01L23/31, H01L23/498, H01L23/538
CPC Code(s): H01L23/5226
Abstract: a stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. the first dielectric layer includes a first via opening. the first conductive via is in the first via opening. a first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. the first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. the second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. the second dielectric layer includes a second via opening. the second conductive via is in the second via opening. the second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.
Inventor(s): Shu-Wei Chung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Sen Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528
CPC Code(s): H01L23/5226
Abstract: a semiconductor structure and method of forming the same are provided. the semiconductor structure has a conductive structure. the semiconductor structure includes a first conductive line, a second conductive line, a third conductive line and a conductive via. the first conductive line and the second conductive line are located in a first dielectric layer and extend along a first direction. the first conductive line and the second conductive line are spaced from each other by the first dielectric layer therebetween. the third conductive line is located in a second dielectric layer and extends along a second direction. the conductive via is vertically between the first conductive line and the third conductive line, and between the second conductive line and the third conductive line. the conductive via, in a vertical direction, is overlapped with a portion of the first dielectric layer that is laterally between the first conductive line and the second conductive line.
Inventor(s): Chung-Shi Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hsun Lee of Chu-tung Town (TW) for taiwan semiconductor manufacturing company, ltd., Jiun Yi Wu of Zhongli (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Cheng Hou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Jen Lin of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Jung Wei Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Ding Wang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Min Liang of Zhongli (TW) for taiwan semiconductor manufacturing company, ltd., Li-Wei Chou of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L21/56, H01L21/683, H01L21/768, H01L23/00, H01L23/31, H01L23/498
CPC Code(s): H01L23/5226
Abstract: an embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. the redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. the third redistribution layer has a third thickness greater than the first thickness and the second thickness. the package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.
Inventor(s): Hiranmay BISWAS of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yeh YU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Nan YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Hsing WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Stefan RUSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Shen LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, G06F30/394, H01L21/768, H01L23/522
CPC Code(s): H01L23/5286
Abstract: a conductive line structure includes: first and second offset sets of long pillars that are substantially coaxial on an intra-set basis; a third set of offset short pillars, the short pillars being: overlapping of long pillars in the first and second sets; and organized into groups of first quantities of the short pillars; each of the groups being overlapping of and electrically coupled between a pair of one of the long pillars in the first set and a one of the long pillars in the second set such that, in each of the groups, each short pillar being overlapping of and electrically coupled between the pair; and each long pillar in each of the first and second sets being overlapped by a second quantity of short pillars in the third set and being electrically coupled to same; and the first quantity being less than the second quantity.
Inventor(s): Fang-Yu Liang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Chiang Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L21/683, H01L23/00, H01L23/31, H01L23/66, H01Q1/22, H01Q9/18, H01Q21/00, H01Q21/06, H01Q21/28, H01Q25/00
CPC Code(s): H01L23/5389
Abstract: a package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. the semiconductor die have an active surface and a backside surface opposite to the active surface. the redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. the antenna patterns are located over the backside surface of the semiconductor die. the die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. the insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.
Inventor(s): Yi-Che Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yuan Sheng Chiu of Miaoli city (TW) for taiwan semiconductor manufacturing company, ltd., Hong-Yu Guo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yu Pan of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Shu Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L25/00, H01L25/10, H01L25/18, H10B80/00
CPC Code(s): H01L23/562
Abstract: an integrated circuit package with a perforated stiffener ring and the method of forming the same are provided. the integrated circuit package may comprise an integrated circuit package component having an integrated circuit die on a substrate, an underfill between the integrated circuit package component and the substrate, and a stiffener ring attached to the substrate. the stiffener ring may encircle the integrated circuit package component and the underfill in a top-down view. the stiffener ring may comprise a perforated region, wherein the perforated region may comprise an array of openings extending from a top surface of the stiffener ring to a bottom surface of the stiffener ring.
Inventor(s): HoChe YU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fong-Yuan CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., XinYong WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Heng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/58, H01L21/765, H01L21/768, H01L23/48, H01L27/02, H01Q9/04
CPC Code(s): H01L23/585
Abstract: a method of making a semiconductor device includes manufacturing an esd cell over a substrate, wherein the esd cell includes multiple diodes connected in parallel to each other. the method includes manufacturing a conductive pillar electrically connected to the esd cell of the semiconductor device; manufacturing a through-silicon via (tsv) extending through the substrate, wherein the tsv extends through the substrate within a tsv zone having a tsv zone perimeter, and wherein a first end of the tsv is at a same side of the substrate as the esd cell, and a second end of the tsv is at a different side of the substrate from the esd cell. the method includes manufacturing an antenna extending parallel to the tsv at a same side of the substrate as the esd cell; and manufacturing an antenna pad electrically connected to the tsv, the antenna, and the conductive pillar.
Inventor(s): Wei-Yu Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Shen Cheng of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Jan Pei of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Philip Yu-Shuan Chung of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Kuei-Wei Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Peng Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiu-Jen Lin of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Shi Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/56, H01L23/31, H01L23/498
CPC Code(s): H01L24/81
Abstract: a method includes performing a first laser shot on a first portion of a top surface of a first package component. the first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. after the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. a second solder region between the first package component and the second package component is reflowed by the second laser shot.
Inventor(s): Po-Hao TSAI of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Da CHENG of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Mirng-Ji LII of Sinpu Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/52, H01L21/56, H01L23/31, H01L23/42, H01L23/538, H01L25/00
CPC Code(s): H01L25/0652
Abstract: a package structure is provided. the package structure includes a substrate including a cavity and a plurality of thermal vias connecting a bottom surface of the cavity to a bottom surface of the substrate. the package structure also includes an electronic device disposed in the cavity and thermally coupled to the plurality of thermal vias. the package structure further includes a plurality of conductive connectors formed over the electronic device and vertically overlapping the plurality of thermal vias. the package structure also includes an encapsulating material extending from top surfaces of the plurality of conductive connectors to the bottom surface of the cavity. the package structure further includes an insulating layer formed over the encapsulating material and including a redistribution layer structure electrically connected to the electronic device through the plurality of conductive connectors.
Inventor(s): Shu-Hang Liao of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wei Wu of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd., Jing-Cheng Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Wei Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Ching Shih of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L21/683, H01L23/00, H01L23/31
CPC Code(s): H01L25/0655
Abstract: a method of forming package structure is provided. the method includes the following steps. a dielectric layer is formed on the first die and the second die. a bridge is placed to electrically connected to the first die and the second die, wherein the dielectric layer is spaced apart from the bridge. an encapsulant is formed on the dielectric layer and laterally encapsulating the bridge. a redistribution layer structure is formed over the encapsulant and the bridge. a top surface of the bridge is in contact with the rdl structure.
Inventor(s): Hao-Yi Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chieh Hsieh of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Hsien Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Chun Chiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Sung Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hung Tseng of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Kris Lipu Chuang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Ming Weng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yuan Yu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tzuan-Horng Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L25/00, H01L25/10
CPC Code(s): H01L25/0657
Abstract: a semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. the first semiconductor die includes a first semiconductor substrate and a through substrate via (tsv) extending from a first side to a second side of the semiconductor substrate. the second semiconductor die is disposed on the first side of the semiconductor substrate. the first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. a terminal of the tsv is coplanar with a surface of the first insulating encapsulation. the dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. the conductor structure extends through the dielectric layer structure and contacts with the through substrate via. the second insulating encapsulation contacts with the second semiconductor die, the first insulting encapsulation, and the dielectric layer structure.
Inventor(s): Tsung-Yuan Yu of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Tzuan-Horng Liu of Longtan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/18, H01L21/56, H01L21/78, H01L23/00, H01L23/31, H01L23/48, H01L23/538, H01L25/00
CPC Code(s): H01L25/18
Abstract: embodiments include a stacked semiconductor device and methods of forming the same. the stacked semiconductor device includes a first package embedded in a second package. forming the first package includes mounting a first integrated circuit device to a first workpiece by a first set of solder connectors, depositing a first underfill between the first integrated circuit device and the first workpiece, and forming a first encapsulant laterally surrounding the first integrated circuit device. the first package is mounted to a second workpiece by a second set of solder connectors, a second underfill is deposited between the first package and the second workpiece, and a second encapsulant is deposited to laterally surround the first package.
Inventor(s): Chien Hung LIU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Sheng CHEN of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yi Ching ONG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsien Jung CHEN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuen-Yi CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ching HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Harry-HakLay CHUANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng WU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Jen WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/18, H01L23/00, H01L23/48, H01L23/522
CPC Code(s): H01L25/18
Abstract: a semiconductor die package includes an inductor-capacitor (lc) semiconductor die that is directly bonded with a logic semiconductor die. the lc semiconductor die includes inductors and capacitors that are integrated into a single die. the inductors and capacitors of the lc semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. the integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
Inventor(s): Wei-Cheng TZENG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Wei PENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Yu HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yen LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng LIN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng TZENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Szuya LIAO of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Chien HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yin WANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Yun WU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, G06F30/392, H01L27/092
CPC Code(s): H01L27/0207
Abstract: an integrated circuit is provided, including a first cell. the first cell includes a first pair of active regions, at least one first gate, two first conductive segments, and a first interconnect structure. the first pair of active regions extends in a first direction and stacked on each other. the at least one first gate extends in a second direction different from the first direction, and is arranged across the first pair of active regions, to form at least one first pair of devices that are stacked on each other. the first conductive segments are coupled to the first pair of active regions respectively. the first interconnect structure is coupled to at least one of a first via or one of the two first conductive segments.
Inventor(s): Tao Yi Hung of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Xuan Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ji Chen of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L23/528
CPC Code(s): H01L27/0255
Abstract: an esd protection device includes a pn diode formed in a semiconductor body. the pn diode has a first contact coupled to a metal structure on a front side of the semiconductor body and a second contact coupled to a metal structure on a back side of the semiconductor body. the metal coupled to the first contact is spaced apart from the metal coupled to the second contact by a thickness of the semiconductor body. this spacing greatly reduces the capacitance associated with the metal structures, which can substantially reduce the overall capacitance added to an i/o channel by the esd protection device and thereby improve the performance of a high-speed circuit that uses the i/o channel.
Inventor(s): Shih-Cheng CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Zhi-Chang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Hung CHANG of Changhua (TW) for taiwan semiconductor manufacturing company, ltd., Lo Heng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., CHIH-HAO WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien Ning YAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/02, H01L21/285, H01L21/8238, H01L29/06, H01L29/423, H01L29/45, H01L29/66, H01L29/786
CPC Code(s): H01L27/0922
Abstract: a semiconductor device structure, along with methods of forming such, are described. the structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. the second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. the structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. the first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.
Inventor(s): Yu-Lien HUANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8234, H01L29/06, H01L29/66, H01L29/78
CPC Code(s): H01L27/0924
Abstract: a device includes a channel layer, a gate structure, a source/drain epitaxial structure, and a gate via. the gate structure is across the channel layer. the gate structure includes a gate dielectric layer and a gate electrode over the gate dielectric layer. the source/drain epitaxial structure is adjacent the gate structure and is electrically connected to the channel layer. the gate via is under the gate structure and is in contact with the gate electrode.
Inventor(s): Chia-Hao Pao of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hsuan Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lien-Jung Hung of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hao Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L27/0924
Abstract: gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. an exemplary metal gate includes a first portion, a second portion, and a third portion. the second portion is disposed between the first portion and the third portion. the first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. the second portion includes a second gate dielectric layer and a second p-type work function layer. the third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. the second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.
Inventor(s): Li-Wen HUANG of Changhua City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Liang CHENG of Changhua City (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Hao LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng LEE of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14623
Abstract: an electrode controls transmittance of a blocking layer over a photodiode of a pixel sensor (e.g., a photodiode of a small pixel detector) by changing oxidation of a metal material included in the blocking layer. by using the electrode to adjust transmittance of the blocking layer, pixel sensors for different uses and/or products may be produced using a single manufacturing process. as a result, power and processing resources are conserved that otherwise would have been expended in switching manufacturing processes. additionally, production time is decreased (e.g., by eliminating downtime that would otherwise have been used to reconfigure fabrication machines.
Inventor(s): Szu-Shu Yang of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Chun Yi Wu of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Kai Tzeng of Neipu Township (TW) for taiwan semiconductor manufacturing company, ltd., Yuh-Sen Chang of Chupei (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Cheng Chen of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Chun Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/08
CPC Code(s): H01L28/10
Abstract: a method of forming a semiconductor device, the method including forming a first insulation layer over a substrate, depositing a first stack of magnetic layers over the first insulation layer, etching the first stack of magnetic layers such that a sidewall of the first stack of magnetic layers forms a stairstep pattern, forming a first photosensitive layer over the first stack of magnetic layers, the first insulation layer, and the substrate, wherein a thickness of the first photosensitive layer above a center of a first step of the stairstep pattern is different from a thickness of the first photosensitive layer above a center of a second step of the stairstep pattern, forming a first conductive feature over the first photosensitive layer, depositing a second insulation layer over the first photosensitive layer and the first conductive feature, and depositing a second magnetic layer over the second insulation layer.
Inventor(s): Wei-Hang Huang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Liang Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146
CPC Code(s): H01L28/91
Abstract: semiconductor structures and methods of forming the same are provided. a semiconductor structure of the present disclosure includes a contact feature disposed in a first dielectric layer, a first etch stop layer (esl) over the contact feature and the first dielectric layer, a second dielectric layer over the first esl, a second esl over the second dielectric layer, a third dielectric layer over the second esl, a third esl over the third dielectric layer, a fourth dielectric layer over the third esl, and a capacitor. the capacitor includes a bottom electrode layer continuously extending along a top surface of the fourth dielectric layer and vertically through the fourth dielectric layer, the third esl, the third dielectric layer, the second esl, the second dielectric layer, and the first esl, an insulator layer disposed over the bottom electrode, and a top electrode layer disposed over the insulator layer.
Inventor(s): Kuan-Ting PAN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Shi-Ning JU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jin CAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L29/423, H01L29/66
CPC Code(s): H01L29/0673
Abstract: a method for forming a semiconductor structure is provided. the method includes forming a first plurality of strip patterns and a second plurality of strip patterns that extend over an epitaxial stack in a first horizontal direction and are alternately arranged in a second horizontal direction perpendicular to the first horizontal direction. the method further includes patterning the first plurality of strip patterns to form a first plurality of island patterns, and patterning the second plurality of strip patterns to form a second plurality of island patterns. the first plurality of island patterns and the second plurality of island patterns are alternately arranged in the second horizontal direction. the method further includes etching the epitaxial stack using the first plurality of island patterns and second plurality of island patterns, thereby forming a fin structure.
Inventor(s): Miao-Syuan FAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Wei LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hua LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Wei LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L21/8234, H01L27/088, H01L29/10, H01L29/40, H01L29/417, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L29/0847
Abstract: the present disclosure relates to a semiconductor device includes first and second source/drain (s/d) regions doped with lead (pb) at a first dopant concentration. the semiconductor device also includes a channel region between the first and second s/d regions, where the channel region is doped with pb at a second dopant concentration that is lower than the first dopant concentration. the semiconductor device further includes first and second s/d contacts in contact with the first and second s/d regions, respectively. the semiconductor device also includes a gate electrode over the channel region.
Inventor(s): Chung-Hui CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Tsun CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Cheng HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8234, H01L21/8238, H01L23/34, H01L27/06, H01L29/08, H01L29/40, H01L29/49, H01L29/66, H01L29/78, H01L29/786
CPC Code(s): H01L29/4175
Abstract: a semiconductor device includes: a first arrangement including first and second silicide layers correspondingly electrically coupled to opposing first and second sides of a doped first portion of an active region; and a second arrangement including a third silicide layer electrically coupled to a first or second side of a doped second portion of the active region.
Inventor(s): Te-Chih Hsiung of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Jyun-De Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chen Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chun Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Tien Tu of Puzih (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/768, H01L21/8234, H01L23/522, H01L23/528, H01L23/532, H01L27/088, H01L29/40, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L29/41791
Abstract: embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. a first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block.
Inventor(s): Te-Chih Hsiung of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Jyun-De Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chen Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chun Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Tien Tu of Puzih (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/768, H01L21/8234, H01L23/522, H01L23/528, H01L23/532, H01L27/088, H01L29/40, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L29/41791
Abstract: the inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.
Inventor(s): Chun-Hsiung TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Feng YU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ting LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Te CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hsiu HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L29/06, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/42392
Abstract: a device includes: a stack of nanostructure channels over a substrate; a gate structure wrapping around the stack; and a source/drain region on the substrate. the source/drain region includes: a first epitaxial layer in direct contact with the channels; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having higher germanium concentration than the first epitaxial layer. the device further includes a bottom isolation structure between the source/drain region and the substrate, the bottom isolation structure being a dielectric layer that is in direct contact with the source/drain region.
Inventor(s): Hsin-Yi Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Lung Hung of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Weng Chang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-On Chui of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/49, H01L21/28, H01L21/285, H01L21/8238, H01L27/092, H01L29/06, H01L29/51, H01L29/66, H01L29/78
CPC Code(s): H01L29/4966
Abstract: semiconductor devices, finfet devices and methods of forming the same are disclosed. one of the semiconductor devices includes a substrate and a gate strip disposed over the substrate. the gate strip includes a high-k layer disposed over the substrate, an n-type work function metal layer disposed over the high-k layer, and a barrier layer disposed over the n-type work function metal layer. the barrier layer includes at least one first film containing tialn, taaln or aln.
Inventor(s): Kuan-Ting PAN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Shi-Ning JU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/28, H01L21/8238, H01L27/092, H01L29/06, H01L29/08, H01L29/423, H01L29/49, H01L29/775
CPC Code(s): H01L29/66439
Abstract: a method for manufacturing a semiconductor structure includes forming fins over a substrate. each of the fins includes a base fin protruding from the substrate, and first semiconductor layers and second semiconductor layers alternating stacked over the base fin. the method further includes forming an isolation structure between the base fins, forming a hard mask layer over the isolation structure, and removing the second semiconductor layers, so that the first semiconductor layers and the hard mask layer are exposed in a gate trench. the method further includes forming a gate structure in the gate trench. the gate structure wraps around the first semiconductor layers and over the hard mask layer.
Inventor(s): Shih-Yao Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiaowen Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Shan Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Cheng Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/764, H01L29/06, H01L29/423, H01L29/786
CPC Code(s): H01L29/6653
Abstract: a method for fabricating semiconductor devices includes forming a channel structure over a substrate and along a first lateral direction; forming a gate structure extending along a second lateral direction and straddling a portion of the channel structure; forming a gate spacer along a side of the gate structure, the gate spacer having a lateral portion and a vertical portion; growing an epitaxial structure over the channel structure; and forming an air gap within the gate spacer. the air gap is entirely above the epitaxial structure and vertically separated from the epitaxial structure by the lateral portion of the gate spacer.
Inventor(s): Yi-Ren CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Hsien CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Ting LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/306, H01L29/423
CPC Code(s): H01L29/6656
Abstract: a semiconductor structure includes a substrate, a channel structure, a gate structure, two gate spacers and an insulating feature. the gate structure is disposed on the channel structure, and includes an upper gate portion which is located at a level higher than that of an uppermost surface of the channel structure. the two gate spacers are respectively located at two opposite sides of the upper gate portion, and each of the gate spacers has an upward surface having a concave profile. the insulating feature is disposed over the upper gate portion and against the concave profiles of the gate spacers to have an inverted u-shaped profile. the insulating feature includes a cap portion which is disposed on an upper surface of the upper gate portion and extends beyond an edge of the upper surface of the upper gate portion. methods for manufacturing the semiconductor structure are also disclosed.
Inventor(s): Shahaji B. MORE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chieh CHANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Han LEE of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Huai-Tei YANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/265, H01L21/3065, H01L29/08, H01L29/167, H01L29/24, H01L29/417, H01L29/78
CPC Code(s): H01L29/66803
Abstract: semiconductor structures and method for forming the same are provide. the method includes forming a fin structure extending in a first direction over a substrate and forming spacers on sidewalls of the fin structure to laterally sandwiched the fin structure in a second direction. the method further includes etching the fin structure in a third direction to form a recess between the spacers and forming a doped region in the fin structure exposed by the recess. the method further includes removing an upper portion of the doped region and annealing a bottom portion of the doped region after removing the upper portion of the doped region. the method further includes forming a source/drain structure over the bottom portion of the doped region.
Inventor(s): Han-Yu LIN of Nantou County (TW) for taiwan semiconductor manufacturing company, ltd., Chansyun David YANG of Shinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fang-Wei LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Chung LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Te LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pinyen LIN of Rochester NY (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/311, H01L21/321, H01L21/768, H01L21/8234, H01L29/06, H01L29/165, H01L29/423, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H01L29/6681
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes forming semiconductor device structure includes a gate stack wrapping around a plurality of nanowire structures. the gate stack includes a first portion above the plurality of nanowire structures and second portions between the nanowire structures. the semiconductor device structure further includes a gate spacer layer along a sidewall of the first portion of the gate stack, and a plurality of inner spacer layers along sidewalls of the second portions of the gate stack. the gate spacer layer has a first carbon concentration, the inner spacer layers have a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.
Inventor(s): Wu-Wei TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Ching CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Wen CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L21/8234, H01L29/417
CPC Code(s): H01L29/78696
Abstract: a semiconductor device includes a gate electrode, a gate dielectric located over the gate electrode, a channel layer including a semiconductor material and located over the gate dielectric, blocking layers located over the channel layer, covering portions of channel layer, and spaced apart from each other, buffer layers respectively located over the blocking layers, respectively surrounded by the blocking layers, and including a material that receives hydrogen, and source/drain contacts respectively located over the buffer layers and respectively surrounded by the buffer layers.
Inventor(s): Ting-Ying Wu of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Hsiang Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Lung Yeh of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Hsiu Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Liang Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ying-Tsang Ho of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/872, H01L29/66
CPC Code(s): H01L29/872
Abstract: a semiconductor device and a method of forming the same is disclosed. the semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. the first well region includes a first type of dopants, the second well region includes a second type of dopants that is different from the first type of dopants, and the array of well regions include the second type of dopants. the semiconductor device further includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer.
Inventor(s): Chen-En Yen of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Da Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Mirng-Ji Lii of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hsiung Lu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Jen Lin of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Wei Kang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Jung Hsueh of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L33/42, H01L23/522, H01L33/60, H01L33/62, H10B63/00
CPC Code(s): H01L33/42
Abstract: a semiconductor device and a manufacturing method thereof are provided. the semiconductor device includes a semiconductor substrate, active devices and transparent conductive patterns. the active devices are formed on the semiconductor substrate. the transparent conductive patterns are formed over the active devices and electrically connected to the active devices. the transparent conductive patterns are made of a metal oxide material. the metal oxide material has a first crystalline phase with a prefer growth plane rich in oxygen vacancy, and has a second crystalline phase with a prefer growth plane poor in oxygen vacancy.
20240235393. POWER MODULE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Ying-Chih Hsu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Eric Soenen of Austin TX (US) for taiwan semiconductor manufacturing company, ltd., Alan Roth of Leander TX (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H02M3/158, H01L25/11, H02M3/155, H03H7/01
CPC Code(s): H02M3/158
Abstract: a power converter module includes a ground terminal, an input voltage terminal configured to receive a raw input voltage, and an interconnection terminal configured to provide a regulated output voltage to a load such as a soc or sip system to be powered. a voltage regulator is connected to the ground terminal and the input voltage terminal. an inductor has an inductor output connected to the interconnection terminal.
Inventor(s): Chih-Chuan Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Ta Yang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Wei Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, G06F30/30, G11C11/412
CPC Code(s): H10B10/00
Abstract: well pick-up (wpu) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. an exemplary semiconductor device includes a circuit region, a first wpu region, second wpu region, a first well of a first conductivity type, and a second well of a second conductivity type. the circuit region, the first wpu region, and the second wpu region are arranged along a first direction in sequence. the first well has a first portion disposed in the circuit region and a second portion disposed in the first wpu region. the second well has a first portion disposed in the circuit region, a second portion disposed in the first wpu region, and a third potion disposed in the second wpu region. measured along the first direction a width of the first wpu region is less than a width of the second wpu region.
Inventor(s): Jheng-Hong JIANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheung CHENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Wei LIU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B63/00, G11C13/00, H10N70/00
CPC Code(s): H10B63/20
Abstract: a memory device includes: a first conductor extending in parallel with a first axis; a first selector material comprising a first portion that extends along a first sidewall of the first conductor; a second selector material comprising a first portion that extends along the first sidewall of the first conductor; a first variable resistive material comprising a portion that extends along the first sidewall of the first conductor; and a second conductor extending in parallel with a second axis substantially perpendicular to the first axis, wherein the first portion of the first selector material, the first potion of the second selector material, and the portion of the first variable resistive material are arranged along a first direction in parallel with a third axis substantially perpendicular to the first axis and second axis.
Inventor(s): Hsin-Hsiang TSENG of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Lin WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Huang WU of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/10, H10N50/01, H10N50/80
CPC Code(s): H10N50/10
Abstract: a memory device includes a bottom electrode, a resistance switching element over the bottom electrode, a top electrode over the resistance switching element, and a dielectric layer. the dielectric layer surrounds the bottom electrode, the resistance switching element, and the top electrode. the resistance switching element has a first portion between the top electrode and the dielectric layer.
Inventor(s): Tai-Yen Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Hsien Wei of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Han-Ting Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sin-Yi Yang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Shu Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., An-Shen Chang of Jubei City (TW) for taiwan semiconductor manufacturing company, ltd., Qiang Fu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Jung Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/80, G11C11/16, H10B61/00, H10N50/01, H10N50/85
CPC Code(s): H10N50/80
Abstract: in an embodiment, a method includes: forming a first inter-metal dielectric (imd) layer over a semiconductor substrate; forming a bottom electrode layer over the first imd layer; forming a magnetic tunnel junction (mtj) film stack over the bottom electrode layer; forming a first top electrode layer over the mtj film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the mtj film stack, the bottom electrode layer, and the first imd layer with an ion beam etching (ibe) process to form a mram cell, where the protective mask is etched during the ibe process.
Inventor(s): Tsung-Hsueh Yang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Chih Huang of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Wen Wang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Ting Sung of Yangmei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/20, H10B63/10, H10N70/00
CPC Code(s): H10N70/231
Abstract: a memory device including a first electrode and a second electrode are over a first dielectric layer. a heater layer is laterally between the first electrode and the second electrode. a thermal transfer layer is over the heater layer. the thermal transfer layer includes a first tapered region between the first electrode and the heater layer. a phase-change layer is over the thermal transfer layer and extends laterally from a top surface of the first electrode to a top surface of the second electrode. the phase-change layer includes a first lateral region over the first electrode and a first step region directly over the first tapered region of the thermal transfer layer. the phase-change layer has a first thickness along the first step region and a second thickness along the first lateral region. a difference between the first thickness and the second thickness is less than 20%.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on July 11th, 2024
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- G02B6/124
- G02B6/12
- G02B6/13
- H01L27/144
- H01L31/0232
- H01L31/028
- H01L31/105
- H01L31/18
- CPC G02B6/124
- Taiwan semiconductor manufacturing company, ltd.
- G02F1/025
- G02F1/21
- G02F1/225
- CPC G02F1/025
- G03F7/00
- C09D1/00
- C09D5/00
- C23C14/06
- C23C14/08
- C23C16/34
- C23C16/40
- CPC G03F7/70316
- CPC G03F7/705
- G06F30/392
- G02B6/122
- G02B27/00
- G05B19/18
- G06F30/39
- G06F30/394
- G06F30/398
- CPC G06F30/392
- G11C7/06
- G11C7/08
- CPC G11C7/065
- G11C7/10
- G06F11/10
- CPC G11C7/1051
- G11C7/22
- G06F7/544
- G11C7/12
- G11C7/14
- G11C7/16
- CPC G11C7/222
- G11C11/22
- H10B51/30
- H10B51/40
- CPC G11C11/2275
- G11C13/00
- CPC G11C13/0038
- H01L21/027
- H01L21/3213
- CPC H01L21/0274
- H01L21/67
- B05D3/06
- H01L21/02
- CPC H01L21/67115
- H01L21/683
- CPC H01L21/6836
- H01L21/687
- CPC H01L21/68742
- H01L21/768
- H01L23/522
- CPC H01L21/76831
- H01L21/822
- H01L21/3065
- H01L21/56
- H01L23/00
- H01L23/31
- H01L25/065
- CPC H01L21/822
- H01L21/8234
- H01L27/088
- H01L21/285
- H01L29/66
- CPC H01L21/82345
- H01L21/3105
- H01L21/762
- H01L29/06
- CPC H01L21/823481
- H01L21/8238
- H01L27/092
- H01L29/40
- H01L29/423
- CPC H01L21/823842
- H01L23/053
- H01L21/52
- H01L25/18
- CPC H01L23/053
- H01L23/42
- H01L23/498
- H01L23/538
- H01L27/06
- CPC H01L23/42
- H01L21/48
- H01L25/00
- H01L25/10
- CPC H01L23/49816
- H01L21/66
- H01L21/78
- CPC H01L23/5226
- H01L23/528
- CPC H01L23/5286
- H01L23/66
- H01Q1/22
- H01Q9/18
- H01Q21/00
- H01Q21/06
- H01Q21/28
- H01Q25/00
- CPC H01L23/5389
- H10B80/00
- CPC H01L23/562
- H01L23/58
- H01L21/765
- H01L23/48
- H01L27/02
- H01Q9/04
- CPC H01L23/585
- CPC H01L24/81
- CPC H01L25/0652
- CPC H01L25/0655
- CPC H01L25/0657
- CPC H01L25/18
- CPC H01L27/0207
- CPC H01L27/0255
- H01L29/45
- H01L29/786
- CPC H01L27/0922
- H01L29/78
- CPC H01L27/0924
- H01L27/146
- CPC H01L27/14623
- H01L27/08
- CPC H01L28/10
- CPC H01L28/91
- CPC H01L29/0673
- H01L29/08
- H01L29/10
- H01L29/417
- CPC H01L29/0847
- H01L23/34
- H01L29/49
- CPC H01L29/4175
- H01L23/532
- CPC H01L29/41791
- H01L29/775
- CPC H01L29/42392
- H01L21/28
- H01L29/51
- CPC H01L29/4966
- CPC H01L29/66439
- H01L21/764
- CPC H01L29/6653
- H01L21/306
- CPC H01L29/6656
- H01L21/265
- H01L29/167
- H01L29/24
- CPC H01L29/66803
- H01L21/311
- H01L21/321
- H01L29/165
- CPC H01L29/6681
- CPC H01L29/78696
- H01L29/872
- CPC H01L29/872
- H01L33/42
- H01L33/60
- H01L33/62
- H10B63/00
- CPC H01L33/42
- H02M3/158
- H01L25/11
- H02M3/155
- H03H7/01
- CPC H02M3/158
- H10B10/00
- G06F30/30
- G11C11/412
- CPC H10B10/00
- H10N70/00
- CPC H10B63/20
- H10N50/10
- H10N50/01
- H10N50/80
- CPC H10N50/10
- G11C11/16
- H10B61/00
- H10N50/85
- CPC H10N50/80
- H10N70/20
- H10B63/10
- CPC H10N70/231
