Sk hynix inc. (20240161861). MEMORY DEVICE PERFORMING TARGET REFRESH OPERATION AND OPERATING METHOD THEREOF simplified abstract

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MEMORY DEVICE PERFORMING TARGET REFRESH OPERATION AND OPERATING METHOD THEREOF

Organization Name

sk hynix inc.

Inventor(s)

Jung Taek You of Gyeonggi-do (KR)

MEMORY DEVICE PERFORMING TARGET REFRESH OPERATION AND OPERATING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240161861 titled 'MEMORY DEVICE PERFORMING TARGET REFRESH OPERATION AND OPERATING METHOD THEREOF

Simplified Explanation

The memory device described in the abstract includes a memory cell region with normal cells, row-hammer cells, and redundancy cells, along with corresponding control circuits for repair and column selection.

  • Memory device with normal cells, row-hammer cells, and redundancy cells
  • Repair control circuit provides repair addresses and row-hammer flag signals based on row address
  • Column control circuit activates redundancy column selection lines based on row-hammer flag signals or comparison result of column address and repair addresses

Potential Applications

The technology described in this patent application could be applied in:

  • Computer memory systems
  • Data storage devices

Problems Solved

This technology addresses issues related to:

  • Row-hammer effects on memory cells
  • Memory cell failures and data loss

Benefits

The benefits of this technology include:

  • Improved reliability of memory devices
  • Enhanced data integrity and security

Potential Commercial Applications

The potential commercial applications of this technology could be in:

  • Consumer electronics
  • Enterprise storage solutions

Possible Prior Art

One possible prior art related to this technology is the use of error correction codes in memory systems to detect and correct data errors.

What are the specific repair addresses provided by the repair control circuit?

The repair control circuit provides repair addresses based on the row address to target specific memory cells for repair.

How does the column control circuit determine which redundancy column selection lines to activate?

The column control circuit activates redundancy column selection lines based on the row-hammer flag signals or by comparing the column address with the repair addresses provided by the repair control circuit.


Original Abstract Submitted

a memory device includes: a memory cell region including normal cells coupled to normal column selection lines, and row-hammer cells and redundancy cells respectively coupled to redundancy column selection lines; a repair control circuit configured to provide repair addresses and row-hammer flag signals, corresponding to repair information, according to a row address; and a column control circuit configured to activate at least one of the redundancy column selection lines according to the row-hammer flag signals or a comparison result of a column address and the repair addresses.