Samsung electronics co., ltd. (20240379639). SEMICONDUCTOR PACKAGE simplified abstract
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Myung Joo Park of Suwon-si (KR)
Hyung Jun Jeon of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240379639 titled 'SEMICONDUCTOR PACKAGE
The semiconductor package described in the abstract includes a structure with a first semiconductor chip, a dummy semiconductor chip, a molding layer, a redistribution layer, through-vias, and a capacitor.
- The first semiconductor chip is electrically connected to the structure and surrounded by the molding layer.
- The dummy semiconductor chip contacts the upper surface of the structure and is also surrounded by the molding layer.
- The redistribution layer is disposed on the upper surface of both the first semiconductor chip and the dummy semiconductor chip.
- The first through-via connects the structure and the redistribution layer through the molding layer.
- The second through-via connects the structure and the redistribution layer through the dummy semiconductor chip.
- A capacitor is located inside the dummy semiconductor chip.
Potential Applications: - This technology can be used in various electronic devices requiring compact and efficient semiconductor packaging. - It can be applied in mobile phones, tablets, laptops, and other consumer electronics.
Problems Solved: - Provides a compact and efficient way to package semiconductor chips. - Enables better electrical connections and signal transmission within electronic devices.
Benefits: - Improved performance and reliability of electronic devices. - Cost-effective manufacturing process for semiconductor packaging.
Commercial Applications: - The technology can be utilized by semiconductor manufacturers to enhance the packaging of their chips, leading to better-performing electronic devices in the market.
Questions about the technology: 1. How does the presence of a dummy semiconductor chip improve the overall performance of the semiconductor package? 2. What are the advantages of having through-vias connecting the structure, semiconductor chips, and redistribution layer in this packaging design?
Original Abstract Submitted
an example semiconductor package includes a structure, a first semiconductor chip disposed on an upper surface of the structure and electrically connected to the structure, a dummy semiconductor chip disposed on and contacting the upper surface of the structure, a molding layer surrounding a sidewall of the first semiconductor chip and a sidewall of the dummy semiconductor chip on the upper surface of the structure, a redistribution layer disposed on an upper surface of the first semiconductor chip, an upper surface of the dummy semiconductor chip, and an upper surface of the molding layer, a first through-via extending through the molding layer in a vertical direction and electrically connecting the structure and the redistribution layer, a second through-via extending through the dummy semiconductor chip in the vertical direction and electrically connecting the structure and the redistribution layer, and a capacitor disposed inside the dummy semiconductor chip.
