Samsung electronics co., ltd. (20240347468). SEMICONDUCTOR PACKAGE simplified abstract
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Myungsam Kang of Hwaseong-si (KR)
Jeongseok Kim of Cheonan-si (KR)
Bongju Cho of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240347468 titled 'SEMICONDUCTOR PACKAGE
The semiconductor package described in the patent application includes a first redistribution structure with a first surface containing embedded first and second pads, as well as a first redistribution layer. Additionally, it features a vertical connection structure comprising a land layer and a pillar layer, with the land layer embedded in the first surface of the first redistribution structure, and the upper surface of the land layer being narrower than the lower surface of the pillar layer.
- The semiconductor package includes a first redistribution structure with embedded pads and a redistribution layer.
- It also features a vertical connection structure with a land layer and a pillar layer.
- The land layer is embedded in the first surface of the first redistribution structure.
- The upper surface of the land layer is narrower than the lower surface of the pillar layer.
Potential Applications: This technology could be used in various semiconductor packaging applications where vertical connections are required, such as in microprocessors, memory devices, and other integrated circuits.
Problems Solved: This technology addresses the need for efficient vertical connections in semiconductor packages, improving overall performance and reliability.
Benefits: - Enhanced vertical connection reliability - Improved performance in semiconductor devices - Increased efficiency in semiconductor packaging processes
Commercial Applications: This technology could have significant commercial applications in the semiconductor industry, particularly in the development of advanced microprocessors, memory devices, and other integrated circuits.
Questions about the technology: 1. How does the width differential between the upper surface of the land layer and the lower surface of the pillar layer impact the performance of the semiconductor package? 2. What are the potential challenges in implementing this technology in mass production processes?
Original Abstract Submitted
a semiconductor package includes a first redistribution structure having a first surface in which a first pad and a second pad are embedded and including a first redistribution layer thereon, and a vertical connection structure including a land layer and a pillar layer. the land layer is embedded in the first surface of the first redistribution structure, and a width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer.
