Samsung electronics co., ltd. (20240339992). LOW POWER MULTIBIT FLIP-FLOP FOR STANDARD CELL LIBRARY simplified abstract
Contents
LOW POWER MULTIBIT FLIP-FLOP FOR STANDARD CELL LIBRARY
Organization Name
Inventor(s)
Mitesh Goyal of Bengaluru (IN)
Hareharan Nagarajan of Bengaluru (IN)
Abhishek Ghosh of Bengaluru (IN)
CHIRANSHU Banthia of Bengaluru (IN)
LOW POWER MULTIBIT FLIP-FLOP FOR STANDARD CELL LIBRARY - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240339992 titled 'LOW POWER MULTIBIT FLIP-FLOP FOR STANDARD CELL LIBRARY
The abstract describes a multibit flip-flop with two stages of one-bit flip-flops that share a common clock signal and use an inter-cell scan input transfer function in a sequential manner. The first stage flip-flop provides a scan output signal based on a scan input signal, while the second stage flip-flop provides a scan final output signal based on the scan output signal from the first stage.
- The multibit flip-flop includes two stages of one-bit flip-flops.
- The stages share a common clock signal for synchronization.
- They use an inter-cell scan input transfer function in a sequential manner.
- The first stage provides a scan output signal based on a scan input signal.
- The second stage provides a scan final output signal based on the scan output signal from the first stage.
Potential Applications: - Integrated circuits - Digital signal processing - Data storage systems
Problems Solved: - Efficient data transfer between flip-flop stages - Synchronization of multiple bits in a multibit flip-flop
Benefits: - Improved performance in digital systems - Enhanced reliability in data storage applications
Commercial Applications: Title: "Advanced Multibit Flip-Flop Technology for High-Speed Data Processing" This technology can be used in high-speed data processing systems, such as in telecommunications, networking equipment, and computer hardware.
Questions about Multibit Flip-Flop Technology: 1. How does the shared clock signal benefit the operation of the multibit flip-flop? 2. What are the advantages of using an inter-cell scan input transfer function in a sequential manner in this technology?
Original Abstract Submitted
a multibit flip flop is provided. the multibit flip flop includes: a first stage one-bit flip flop; and a second stage one-bit flip flop, wherein the first stage one-bit flip flop and the second stage one-bit flip flop are configured to share a common clock signal. the first stage one-bit flip flop and the second stage one-bit flip flop are configured to use an inter cell scan input transfer function in a sequential manner. the first stage one-bit flip flop is further configured to provide a scan output signal based on a scan input signal provided at an input port of the first stage one-bit flip flop. the second stage one-bit flip flop is further configured to provide a scan final output signal based on the scan output signal that is provided at an input port of the second stage one-bit flip flop.
