Samsung electronics co., ltd. (20240322048). INTERGRATED CIRCUIT DEVICES simplified abstract
Contents
INTERGRATED CIRCUIT DEVICES
Organization Name
Inventor(s)
Kyunghwan Lee of Suwon-si (KR)
INTERGRATED CIRCUIT DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240322048 titled 'INTERGRATED CIRCUIT DEVICES
The abstract describes an integrated circuit device with a unique structure that includes a source line, channel layer, trapping layer, word line, gate insulation layer, and bit line.
- Source line extends horizontally on a substrate.
- Channel layer extends vertically and has two sidewalls.
- Trapping layer, with an oxide semiconductor, is on one sidewall of the channel layer.
- Word line crosses the source line horizontally and is on the trapping layer.
- Gate insulation layer separates the word line and trapping layer.
- Bit line is connected to the channel layer and extends horizontally.
- Trapping layer has a higher bandgap energy than the channel layer.
- Key Features and Innovation:**
- Unique structure with trapping layer on the sidewall of the channel layer.
- Word line crossing the source line at a right angle.
- Trapping layer with higher bandgap energy for improved performance.
- Potential Applications:**
- Memory devices.
- Logic circuits.
- Microprocessors.
- Problems Solved:**
- Enhanced performance and efficiency.
- Improved data storage and processing capabilities.
- Benefits:**
- Higher speed and reliability.
- Lower power consumption.
- Increased data storage capacity.
- Commercial Applications:**
- Semiconductor industry for memory and logic devices.
- Electronics manufacturing for improved integrated circuits.
- Questions about the Technology:**
1. How does the trapping layer with higher bandgap energy improve the performance of the integrated circuit device? 2. What are the potential challenges in scaling this technology for mass production?
Original Abstract Submitted
provided is an integrated circuit device including a source line extending in a first horizontal direction on a substrate, a channel layer extending in a vertical direction, disposed on the source line, and having a first sidewall and a second sidewall, a trapping layer on the first sidewall of the channel layer and including an oxide semiconductor, a word line on at least one sidewall of the trapping layer and extending in a second horizontal direction crossing the first horizontal direction, a gate insulation layer between the at least one sidewall of the trapping layer and the word line, and a bit line electrically connected to the channel layer and extending in the first horizontal direction, wherein the channel layer has a first bandgap energy, and the trapping layer has a second bandgap energy that is greater than the first bandgap energy.
