Samsung electronics co., ltd. (20240321840). THREE-DIMENSIONAL SEMICONDUCTOR PACKAGE simplified abstract
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THREE-DIMENSIONAL SEMICONDUCTOR PACKAGE
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THREE-DIMENSIONAL SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240321840 titled 'THREE-DIMENSIONAL SEMICONDUCTOR PACKAGE
The abstract describes a three-dimensional semiconductor package consisting of a package substrate with two surfaces, a first redistribution layer on the first surface, a first chip on the first redistribution layer, first connection terminals, a second redistribution layer on the second surface, and a second chip on the second redistribution layer.
- Package includes a package substrate, first and second redistribution layers, and two chips.
- First chip is on the first redistribution layer and connected to it through first through silicon vias.
- First connection terminals are connected to one end of the first through silicon vias.
- Second chip is on the second redistribution layer on the second surface of the package substrate.
Potential Applications: - Advanced semiconductor packaging technology for high-performance electronic devices. - Suitable for applications requiring compact and efficient three-dimensional integration of chips.
Problems Solved: - Enables dense integration of chips in a three-dimensional configuration. - Facilitates efficient electrical connections between chips and redistribution layers.
Benefits: - Improved performance and functionality of electronic devices. - Enhanced thermal management and signal integrity in semiconductor packages.
Commercial Applications: Title: Advanced Three-Dimensional Semiconductor Packaging Technology This technology can be utilized in the development of high-performance computing devices, mobile phones, IoT devices, and other electronic systems requiring compact and efficient chip integration.
Questions about Three-Dimensional Semiconductor Package: 1. How does the three-dimensional configuration of the semiconductor package contribute to its performance?
- The three-dimensional configuration allows for dense integration of chips, reducing signal delays and improving overall efficiency.
2. What are the key advantages of using through silicon vias in semiconductor packaging?
- Through silicon vias enable vertical connections between different layers, enhancing the electrical performance and compactness of the package.
Original Abstract Submitted
a three-dimensional semiconductor package including: a package substrate having a first surface and a second surface opposite to the first surface; a first redistribution layer on the first surface of the package substrate, the first redistribution layer having a first surface and a second surface opposite to each other; a first chip on the first surface of the first redistribution layer, electrically connected to the first redistribution layer, and including first through silicon vias; first connection terminals electrically connected to one ends of the first through silicon vias; a second redistribution layer on the second surface of the package substrate, the second redistribution layer having a first surface and a second surface opposite to each other, the first surface of the second redistribution layer facing the second surface of the package substrate; and a second chip on the second surface of the second redistribution layer.
