Samsung electronics co., ltd. (20240297139). SEMICONDUCTOR PACKAGE simplified abstract
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240297139 titled 'SEMICONDUCTOR PACKAGE
The semiconductor package described in the abstract includes a package substrate with a recessed portion on the top surface, a lower semiconductor chip placed in the recessed portion, an upper semiconductor chip on top of the lower chip and the package substrate, with a width greater than that of the lower chip. The package also features first bumps between the package substrate and the upper chip, as well as second bumps between the lower chip and the upper chip, with the pitch of the second bumps being smaller than that of the first bumps.
- Package substrate with recessed portion
- Lower semiconductor chip in the recessed portion
- Upper semiconductor chip on top of lower chip and substrate
- First bumps between package substrate and upper chip
- Second bumps between lower chip and upper chip, with smaller pitch
Potential Applications: - Advanced semiconductor packaging technology - High-density integrated circuits - Miniaturized electronic devices
Problems Solved: - Improved thermal management - Enhanced electrical connectivity - Increased packaging density
Benefits: - Higher performance in compact devices - Improved reliability and durability - Enhanced overall functionality
Commercial Applications: Title: Advanced Semiconductor Packaging Technology for High-Density Integrated Circuits This technology can be utilized in various industries such as consumer electronics, telecommunications, automotive, and aerospace for the development of smaller, more efficient electronic devices with increased performance capabilities.
Questions about the technology: 1. How does the pitch of the second bumps affect the overall performance of the semiconductor package? 2. What are the specific advantages of having an upper semiconductor chip with a width greater than that of the lower chip?
Original Abstract Submitted
a semiconductor package comprising a package substrate that has a recessed portion on a top surface thereof, a lower semiconductor chip in the recessed portion of the package substrate, an upper semiconductor chip on the lower semiconductor chip and the package substrate and having a width greater than that of the lower semiconductor chip, a plurality of first bumps directly between the package substrate and the upper semiconductor chip, and a plurality of second bumps directly between the lower semiconductor chip and the upper semiconductor chip. a pitch of the second bumps is less than that of the first bumps.
