Samsung electronics co., ltd. (20240243111). SEMICONDUCTOR PACKAGE simplified abstract
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SeungRyong Oh of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240243111 titled 'SEMICONDUCTOR PACKAGE
The semiconductor package described in the abstract consists of a lower package and an upper package on top of the lower package. The lower package contains a first substrate, chip stacks, a first mold structure, and a second substrate.
- The chip stacks in the lower package consist of a first semiconductor chip and a second semiconductor chip stacked on top of the first semiconductor chip.
- The first semiconductor chip includes a semiconductor substrate, a wiring layer with wiring patterns, a circuit layer with a transistor and circuit wirings, and a chip through electrode that penetrates the circuit layer and the semiconductor substrate.
- The height of the chip through electrode ranges from 2 µm to 50 µm.
Potential Applications:
- This semiconductor package technology can be used in various electronic devices such as smartphones, tablets, and laptops.
- It can also be applied in automotive electronics, medical devices, and industrial equipment.
Problems Solved:
- This technology addresses the need for compact and efficient semiconductor packaging solutions.
- It provides a way to stack multiple semiconductor chips in a small space while maintaining proper electrical connections.
Benefits:
- Improved performance and functionality of electronic devices.
- Enhanced reliability and durability of semiconductor packages.
- Cost-effective manufacturing processes for semiconductor packaging.
Commercial Applications:
- The technology can be utilized by semiconductor manufacturers, electronics companies, and other industries requiring advanced packaging solutions.
Questions about the technology: 1. How does the height range of the chip through electrode impact the performance of the semiconductor package? 2. What are the specific advantages of stacking multiple semiconductor chips in a single package?
Frequently Updated Research:
- Stay updated on the latest advancements in semiconductor packaging technology to ensure optimal performance and reliability in electronic devices.
Original Abstract Submitted
a semiconductor package includes a lower package and an upper package on the lower package. the lower package includes a first substrate, chip stacks on the first substrate, a first mold structure on the first substrate that covers the chip stacks, and a second substrate on the first mold structure. the chip stacks include a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. the first semiconductor chip includes a first semiconductor substrate, a first wiring layer adjacent the first semiconductor substrate and including wiring patterns, a first circuit layer on the first semiconductor substrate and including a transistor and circuit wirings connected to the transistor, and a chip through electrode penetrating at least a portion of the first circuit layer and the first semiconductor substrate and a height of the chip through electrode ranges from 2 �m to 50 �m.
