Samsung electronics co., ltd. (20240243110). SEMICONDUCTOR PACKAGE simplified abstract
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
HYEONJEONG Hwang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240243110 titled 'SEMICONDUCTOR PACKAGE
The semiconductor package described in the patent application includes an interposer substrate, a chip stack with vertically stacked first semiconductor chips, a second semiconductor chip horizontally spaced apart from the chip stack, a molding layer surrounding the chip stack and the second semiconductor chip, a redistribution layer on the molding layer, and conductive posts connecting the interposer substrate to the redistribution layer.
- Interposer substrate
- Chip stack with vertically stacked first semiconductor chips
- Second semiconductor chip horizontally spaced apart from the chip stack
- Molding layer surrounding the chip stack and second semiconductor chip
- Redistribution layer on the molding layer
- Conductive posts connecting the interposer substrate to the redistribution layer
Potential Applications: - Advanced semiconductor packaging technology - High-density integrated circuits - Improved performance and reliability in electronic devices
Problems Solved: - Enhancing connectivity and signal transmission in semiconductor packages - Increasing packaging density without sacrificing performance - Addressing thermal management challenges in stacked chip configurations
Benefits: - Higher integration levels in semiconductor devices - Improved electrical performance and signal integrity - Enhanced thermal dissipation capabilities
Commercial Applications: Title: Advanced Semiconductor Packaging Technology for High-Performance Electronics This technology can be applied in various industries such as telecommunications, computing, automotive, and consumer electronics for high-performance and compact electronic devices.
Questions about the technology: 1. How does the semiconductor package described in the patent application improve signal transmission efficiency? 2. What are the key advantages of using conductive posts to connect the interposer substrate to the redistribution layer?
Original Abstract Submitted
disclosed is a semiconductor package comprising an interposer substrate, a chip stack on the interposer substrate and including first semiconductor chips that are vertically stacked, a second semiconductor chip on the interposer substrate and horizontally spaced apart from the chip stack, a molding layer on the interposer substrate and surrounding the chip stack and the second semiconductor chip, a redistribution layer on the molding layer, and a plurality of conductive posts that vertically penetrate the molding layer and connect the interposer substrate to the redistribution layer.
