Samsung electronics co., ltd. (20240213268). CHIP ON FILM PACKAGE AND DISPLAY APPARATUS INCLUDING THE SAME simplified abstract
Contents
CHIP ON FILM PACKAGE AND DISPLAY APPARATUS INCLUDING THE SAME
Organization Name
Inventor(s)
CHIP ON FILM PACKAGE AND DISPLAY APPARATUS INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240213268 titled 'CHIP ON FILM PACKAGE AND DISPLAY APPARATUS INCLUDING THE SAME
The chip on film package described in the patent application includes a film substrate with an upper layer extending in opposite directions and a lower layer with a cutting line. Two semiconductor chips are placed on the upper layer within the cutting line area, along with connection wirings extending in different directions and a test pad on the lower layer within the cutting line area.
- Film substrate with upper and lower layers
- Semiconductor chips placed within cutting line area
- Connection wirings extending in different directions
- Test pad on lower layer within cutting line area
Potential Applications: - Semiconductor packaging - Electronics manufacturing
Problems Solved: - Efficient chip placement and connection in a compact package
Benefits: - Space-saving design - Simplified manufacturing process
Commercial Applications: - Semiconductor industry - Electronics packaging companies
Questions about chip on film package: 1. How does the cutting line on the lower layer impact the overall design of the package? 2. What are the advantages of having connection wirings extending in different directions?
Frequently Updated Research: - Ongoing advancements in semiconductor packaging technologies may impact the design and efficiency of chip on film packages.
Original Abstract Submitted
there is provided a chip on film package. the chip on film package includes a film substrate including an upper layer extending in first and second directions opposite to each other and a lower layer facing the upper layer, and having a cutting line formed thereon, first and second semiconductor chips disposed on the upper layer within an area of the cutting line, first and second connection wirings connected to the first and second semiconductor chips and extending toward the first and second directions, respectively, and a test pad connected to at least one of the first and second connection wirings and disposed on the lower layer, within the area of the cutting line.
