Samsung electronics co., ltd. (20240203939). SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Organization Name
Inventor(s)
Hyunsoo Chung of Suwon-si (KR)
Won-Young Kim of Suwon-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240203939 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
The semiconductor package described in the patent application includes a power delivery network, a semiconductor chip on the top surface of the power delivery network, and a second semiconductor chip horizontally spaced from the first chip on the top surface.
- The first chip has first and second surfaces, while the second chip has third and fourth surfaces.
- Chip stacks are present on both the first and second semiconductor chips.
- The first surface of the first chip is an active surface, while the third surface of the second chip is also an active surface.
- The first chip stack includes third semiconductor chips with their active surfaces facing the first semiconductor chip.
- The first chip stack and the second semiconductor chip can be electrically connected through the power delivery network.
Potential Applications: - This technology can be used in high-performance computing systems. - It can also be applied in advanced consumer electronics devices.
Problems Solved: - Improved electrical connectivity between semiconductor chips. - Enhanced performance and efficiency in semiconductor packages.
Benefits: - Increased data processing speed. - Better thermal management. - Higher reliability in electronic devices.
Commercial Applications: Title: Advanced Semiconductor Packaging for High-Performance Computing Systems This technology can be utilized in data centers, supercomputers, and other high-performance computing applications to enhance processing power and efficiency.
Questions about the technology: 1. How does the power delivery network improve the performance of the semiconductor package? 2. What are the advantages of having chip stacks on both the first and second semiconductor chips?
Original Abstract Submitted
a semiconductor package includes a power delivery network, a semiconductor chip on a top surface of the power delivery network, and having first and second surfaces opposite to each other, a second semiconductor chip on the top surface horizontally spaced from the first semiconductor chip, the second semiconductor chip having third surface and fourth surfaces, opposite to each other, chip stacks on the first semiconductor chip, and on the second semiconductor chip. the first surface is an active surface. the third surface is an active surface of the second semiconductor chip. the first chip stack includes third semiconductor chips on the first surface of the first semiconductor chip. the third semiconductor chips is disposed such that an active surface thereof faces the first semiconductor chip, and the first chip stack and the second semiconductor chip may be electrically connected to each other through the power delivery network.
