Samsung electronics co., ltd. (20240202424). METHOD OF CORRECTING DESIGN LAYOUT OF SEMICONDUCTOR DEVICE, COMPUTING DEVICE PERFORMING THE SAME, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME simplified abstract
METHOD OF CORRECTING DESIGN LAYOUT OF SEMICONDUCTOR DEVICE, COMPUTING DEVICE PERFORMING THE SAME, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME
Organization Name
Inventor(s)
Hyuckjoon Kwon of Suwon-si (KR)
METHOD OF CORRECTING DESIGN LAYOUT OF SEMICONDUCTOR DEVICE, COMPUTING DEVICE PERFORMING THE SAME, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240202424 titled 'METHOD OF CORRECTING DESIGN LAYOUT OF SEMICONDUCTOR DEVICE, COMPUTING DEVICE PERFORMING THE SAME, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME
Simplified Explanation: A computing device adjusts target patterns in a layer based on misalignment values to correct a design layout.
Key Features and Innovation:
- Separation of target patterns from an original design layout
- Shifting of target patterns based on misalignment values
- Generation of a corrected design layout by combining adjusted target patterns with the original layout
Potential Applications: This technology can be used in the semiconductor industry for improving the accuracy of design layouts in integrated circuits.
Problems Solved: The technology addresses issues related to misalignment of target patterns in design layouts, which can lead to errors in the final product.
Benefits:
- Enhanced accuracy in design layouts
- Improved quality control in manufacturing processes
- Reduction of errors and defects in integrated circuits
Commercial Applications: The technology has significant commercial potential in the semiconductor industry, where precise design layouts are crucial for product performance and reliability.
Prior Art: Researchers can explore prior art related to design layout correction algorithms and semiconductor manufacturing processes.
Frequently Updated Research: Ongoing research in the field of design layout optimization and semiconductor manufacturing may provide further insights into the development and application of this technology.
Questions about Design Layout Correction: 1. How does this technology contribute to the efficiency of semiconductor manufacturing processes? 2. What are the potential implications of using this technology in other industries besides semiconductors?
Original Abstract Submitted
a computing device separates a first target layer including a plurality of target patterns from an original design layout, shifts the plurality of target patterns in the first target layer based on misalignment values at positions of the plurality of target patterns to generate a second target layer, and combines the second target layer with the original design layout from which the first target layer is separated to generate a corrected design layout.
