Samsung electronics co., ltd. (20240188293). SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME simplified abstract

SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME

Organization Name

samsung electronics co., ltd.

Inventor(s)

Sam Ki Kim of Suwon-si (KR)

Nam Bin Kim of Suwon-si (KR)

Ji Woong Kim of Suwon-si (KR)

Tae Hun Kim of Suwon-si (KR)

Ki Bong Moon of Suwon-si (KR)

Sae Rom Lee of Suwon-si (KR)

Sung-Bok Lee of Suwon-si (KR)

Jun Hee Lim of Suwon-si (KR)

Nag Yong Choi of Suwon-si (KR)

Sun Gyung Hwang of Suwon-si (KR)

SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240188293 titled 'SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME

Simplified Explanation

The semiconductor memory device described in the patent application includes a unique mold structure with gate electrodes and mold insulating layers stacked in a stair shape, channel structures on the substrate intersecting the gate electrodes, cell contacts connected to the gate electrodes, metal patterns connected to the channel structures and cell contacts, a blocking layer, and dummy vias passing through the blocking layer.

• Mold structure with gate electrodes and mold insulating layers in a stair shape
• Channel structures intersecting gate electrodes and passing through mold structure
• Cell contacts connected to gate electrodes
• Metal patterns connected to channel structures and cell contacts
• Blocking layer along upper surface of interlayer insulating layer, metal patterns, and cell contacts
• Dummy vias passing through blocking layer

Potential Applications

The technology described in this patent application could be applied in various semiconductor memory devices, such as flash memory, DRAM, and SRAM.

Problems Solved

This technology solves the problem of improving the performance and efficiency of semiconductor memory devices by optimizing the layout and structure of the components.

Benefits

The benefits of this technology include increased memory device performance, enhanced data storage capacity, and improved reliability and durability.

Potential Commercial Applications

The technology could be utilized in the production of advanced semiconductor memory devices for various electronic devices, such as smartphones, tablets, computers, and servers.

Possible Prior Art

One possible prior art for this technology could be the use of similar mold structures and metal patterns in semiconductor memory devices, but with different configurations and layouts.

How does this technology compare to existing semiconductor memory devices in terms of performance and efficiency?

The article does not provide a direct comparison between this technology and existing semiconductor memory devices in terms of performance and efficiency.

What are the specific manufacturing processes involved in producing this semiconductor memory device?

The article does not delve into the specific manufacturing processes involved in producing this semiconductor memory device.

Original Abstract Submitted

a semiconductor memory device including a substrate; a mold structure including gate electrodes and mold insulating layers stacked in a stair shape, channel structures on the substrate, intersecting the gate electrodes, and passing through the mold structure; cell contacts connected to the gate electrodes; a first interlayer insulating layer on the mold structure and covering the channel structures and cell contacts; first metal patterns connected to the channel structures, an upper surface of the first metal patterns being coplanar with an upper surface of the first interlayer insulating layer; second metal patterns connected to the cell contacts, an upper surface of the second metal patterns being coplanar with the upper surface of the first metal patterns; a first blocking layer along the upper surface of the first interlayer insulating layer, the first metal patterns, and the second metal patterns; and a first dummy vias passing through the first blocking layer.