Samsung electronics co., ltd. (20240186290). SEMICONDUCTOR PACKAGE simplified abstract
Contents
- 1 SEMICONDUCTOR PACKAGE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Youngdeuk Kim of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240186290 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes multiple vertically stacked semiconductor chips with an encapsulant covering them. External connection bumps are located below the first semiconductor chip and are electrically connected to the chips. Each semiconductor chip has lower pads, upper pads (including two groups), and through-electrodes connecting the upper and lower pads.
- The semiconductor package consists of multiple semiconductor chips stacked vertically.
- An encapsulant covers the semiconductor chips to protect them.
- External connection bumps below the first chip provide electrical connections.
- Each semiconductor chip has lower pads, upper pads (divided into two groups), and through-electrodes connecting them.
Potential Applications
The technology described in this patent application could be used in various electronic devices such as smartphones, tablets, laptops, and other portable electronics that require compact and efficient semiconductor packaging.
Problems Solved
This technology solves the problem of efficiently stacking multiple semiconductor chips in a vertical direction while ensuring proper electrical connections between them. It also addresses the issue of protecting the semiconductor chips from external elements with the encapsulant.
Benefits
The benefits of this technology include increased packaging density, improved electrical connectivity, and enhanced protection for the semiconductor chips. Additionally, the vertical stacking design allows for more efficient use of space in electronic devices.
Potential Commercial Applications
- "Vertical Semiconductor Chip Stacking Technology for Compact Electronic Devices"
Possible Prior Art
One possible prior art for this technology could be the use of through-silicon vias (TSVs) in semiconductor packaging to enable vertical stacking of chips. Another could be the use of multi-chip modules (MCMs) for compact electronic devices.
Unanswered Questions
How does this technology compare to traditional horizontal semiconductor chip packaging methods in terms of performance and efficiency?
This article does not provide a direct comparison between vertical stacking and traditional horizontal packaging methods.
What are the specific materials used for the encapsulant in this semiconductor package?
The abstract does not mention the specific materials used for the encapsulant covering the semiconductor chips.
Original Abstract Submitted
a semiconductor package includes electrically connected first to third semiconductor chips, stacked in a vertical direction; an encapsulant on the first semiconductor chip and encapsulating a portion of each of the semiconductor chips; and external connection bumps below the first semiconductor chip and being electrically connected to the semiconductor chips, wherein the semiconductor chips each include a plurality of lower pads, the first and second semiconductor chips each include a plurality of upper pads including a first group of upper pads and a second group of upper pads, and through-electrodes electrically respectively connecting the upper pads and the lower pads, and the through-electrodes include a first group of through-electrodes respectively connected to the first group of upper pads, and a second group of through-electrodes connected to upper pads that are electrically connected to each other of the second group of upper pads.
