Samsung electronics co., ltd. (20240186289). SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE simplified abstract

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SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

Organization Name

samsung electronics co., ltd.

Inventor(s)

Hanmin Lee of Suwon-si (KR)

Unbyoung Kang of Suwon-si (KR)

Seongyo Kim of Suwon-si (KR)

Sangsick Park of Suwon-si (KR)

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240186289 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

Simplified Explanation

The method described in the patent application involves manufacturing a semiconductor package by stacking memory dies using an adhesive member, forming molding members to cover the memory die stack, polishing the upper surface to expose the uppermost memory die, removing edge portions of the uppermost memory die to create a stepped portion, and forming a second molding member to cover the stepped portion.

  • Stacking memory dies using an adhesive member
  • Forming molding members to cover the memory die stack
  • Polishing the upper surface to expose the uppermost memory die
  • Removing edge portions of the uppermost memory die to create a stepped portion
  • Forming a second molding member to cover the stepped portion

Potential Applications

The technology described in this patent application could be applied in the manufacturing of advanced semiconductor packages for various electronic devices such as smartphones, tablets, and computers.

Problems Solved

This technology solves the problem of efficiently stacking and protecting memory dies in a semiconductor package while ensuring proper functionality and durability.

Benefits

The benefits of this technology include improved memory die stacking efficiency, enhanced protection of memory dies, and overall increased reliability of semiconductor packages.

Potential Commercial Applications

  • "Innovative Semiconductor Package Manufacturing Method for Enhanced Memory Die Stacking Efficiency"

Possible Prior Art

One possible prior art could be the traditional methods of stacking memory dies in semiconductor packages, which may not involve the specific steps outlined in this patent application.

Unanswered Questions

How does this method compare to existing semiconductor packaging techniques?

The article does not provide a direct comparison to existing semiconductor packaging techniques, leaving room for further analysis on the advantages and disadvantages of this method.

What are the specific materials used for the adhesive and molding members in this method?

The article does not specify the exact materials used for the adhesive and molding members, which could be crucial information for understanding the feasibility and performance of this manufacturing process.


Original Abstract Submitted

a method of manufacturing a semiconductor package comprises stacking, via an adhesive member, a plurality of memory dies to form a memory die stack on a buffer die; forming a first molding member on the buffer die to cover the memory die stack; polishing an upper surface of the first molding member to expose an upper surface of an uppermost memory die in the memory die stack, the uppermost memory die positioned in an uppermost layer in the memory die stack; removing edge portions of the uppermost memory die together with at least a portion of the first molding member and at least a portion of the adhesive member to form a stepped portion; and forming a second molding member on the first molding member to cover the stepped portion of the uppermost memory die.