Samsung electronics co., ltd. (20240178176). SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE simplified abstract
Contents
- 1 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
DONGHYEON Jang of SUWON-SI (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240178176 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in the abstract includes multiple layers of redistribution wirings, a semiconductor chip, a sealing member, through vias, and an upper redistribution wiring layer. Each of the first redistribution wirings is composed of a barrier layer pattern, a seed layer pattern, and a plating pattern stacked sequentially. The barrier layer pattern extends laterally beyond the seed layer pattern in a plan view.
- Lower redistribution wiring layer with stacked first redistribution wirings
- Semiconductor chip electrically connected to first redistribution wirings
- Sealing member covering the semiconductor chip
- Through vias penetrating the sealing member and connected to first redistribution wirings
- Upper redistribution wiring layer with second redistribution wirings connected to through vias
Potential Applications
This technology can be applied in the manufacturing of advanced semiconductor packages for various electronic devices such as smartphones, tablets, and computers.
Problems Solved
This technology solves the problem of efficiently routing and connecting multiple layers of redistribution wirings in a semiconductor package, improving overall performance and reliability.
Benefits
The benefits of this technology include enhanced electrical connectivity, increased packaging density, improved signal integrity, and overall cost-effectiveness in semiconductor packaging.
Potential Commercial Applications
The potential commercial applications of this technology include the semiconductor industry, electronics manufacturing companies, and suppliers of advanced packaging solutions.
Possible Prior Art
One possible prior art in semiconductor packaging technology is the use of multi-layer redistribution wirings with through vias for improved electrical connections and signal transmission.
Unanswered Questions
1. How does this technology compare to existing methods of semiconductor packaging in terms of performance and cost? 2. Are there any limitations or challenges in implementing this technology on a large scale in semiconductor manufacturing processes?
Original Abstract Submitted
a semiconductor package includes a lower redistribution wiring layer having first redistribution wirings stacked in at least two layers, a semiconductor chip disposed on the lower redistribution wiring layer and electrically connected to the first redistribution wirings, a sealing member covering the semiconductor chip on the lower redistribution wiring layer, a plurality of through vias penetrating the sealing member and electrically connected to the first redistribution wirings, and an upper redistribution wiring layer disposed on the sealing member and having second redistribution wirings electrically connected to the plurality of through vias. each of the first redistribution wirings includes a barrier layer pattern, a seed layer pattern and a plating pattern sequentially stacked. from a plan view, a sidewall of the barrier layer pattern extends laterally beyond a sidewall of the seed layer pattern.
