Samsung electronics co., ltd. (20240178117). SEMICONDUCTOR PACKAGES simplified abstract

SEMICONDUCTOR PACKAGES

Organization Name

samsung electronics co., ltd.

Inventor(s)

Myung Sam Kang of Suwon-si (KR)

SEMICONDUCTOR PACKAGES - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240178117 titled 'SEMICONDUCTOR PACKAGES

Simplified Explanation

The semiconductor package described in the patent application includes a glass core with a through via, a connection module, and multiple redistribution layers to facilitate electrical connections between semiconductor chips.

• The semiconductor package comprises a glass core with a through via for electrical connections.
• A connection module is located on the upper surface of the first redistribution layer.
• Multiple redistribution layers, including via pads, are used to connect semiconductor chips.
• The first and second semiconductor chips are spaced apart on the upper surface of the second redistribution layer.
• The connection module enables electrical connection between the first and second semiconductor chips.

Potential Applications

The technology described in this patent application could be applied in various semiconductor devices, such as microprocessors, memory chips, and integrated circuits.

Problems Solved

This technology solves the problem of efficiently connecting multiple semiconductor chips in a compact and reliable manner, reducing the overall size of semiconductor packages.

Benefits

The benefits of this technology include improved electrical connections, reduced package size, and enhanced overall performance of semiconductor devices.

Potential Commercial Applications

This innovative semiconductor packaging technology could be utilized in the manufacturing of consumer electronics, automotive electronics, telecommunications equipment, and other electronic devices.

Possible Prior Art

One possible prior art for this technology could be the use of multilayer ceramic substrates in semiconductor packaging to facilitate electrical connections between chips.

How does this technology compare to traditional semiconductor packaging methods?

This article does not provide a direct comparison between this innovative semiconductor packaging technology and traditional methods.

What are the specific materials used in the glass core and redistribution layers?

The article does not specify the exact materials used in the glass core and redistribution layers.

Original Abstract Submitted

a semiconductor package comprises a first redistribution layer including a first conductive pattern; a connection module on an upper surface of the first redistribution layer; a glass core extending around the connection module on the upper surface of the first redistribution layer; a through via extended in the glass core; a second insulating layer on the glass core, wherein a portion of the second insulating layer is in the through via; a second redistribution layer on an upper surface of the glass core, wherein the second redistribution layer includes a via pad; and a first semiconductor chip and a second semiconductor chip space apart from each other on an upper surface of the second redistribution layer, wherein the via pad is in contact with the through via, and wherein the first semiconductor chip and the second semiconductor chip are electrically connected to each other through the connection module.