Samsung electronics co., ltd. (20240162194). SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Organization Name

samsung electronics co., ltd.

Inventor(s)

Jaekyung Yoo of Seoul (KR)

Jayeon Lee of Seongnam-si (KR)

Jae-eun Lee of Hwaseong-si (KR)

Yeongkwon Ko of Hwaseong-si (KR)

Jin-woo Park of Seoul (KR)

Teak Hoon Lee of Hwaseong-si (KR)

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240162194 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Simplified Explanation

The semiconductor package described in the patent application includes a package substrate, a first semiconductor chip, a second semiconductor chip, and a first under-fill layer. The package substrate has a cavity and a vent hole in fluid communication with the cavity. The first under-fill layer fills the space between the package substrate and the first semiconductor chip, extending along the vent hole to fill the cavity.

• Package substrate with cavity and vent hole
• First semiconductor chip mounted on package substrate
• Second semiconductor chip mounted on top of first chip
• First under-fill layer filling space between substrate and first chip
• First under-fill layer extends along vent hole to fill cavity

Potential Applications

The technology described in this patent application could be applied in the semiconductor industry for the fabrication of advanced semiconductor packages with improved thermal management and reliability.

Problems Solved

This technology solves the problem of thermal dissipation and mechanical stress in semiconductor packages by providing a structure that efficiently fills the space between the chips and the substrate.

Benefits

The benefits of this technology include enhanced thermal performance, increased reliability, and improved overall performance of semiconductor devices.

Potential Commercial Applications

The potential commercial applications of this technology could include the production of high-performance computing devices, mobile devices, automotive electronics, and other advanced electronic systems.

Possible Prior Art

One possible prior art for this technology could be the use of under-fill materials in semiconductor packaging to improve thermal management and reliability. Another could be the integration of multiple chips in a single package to increase functionality and performance.

How does the size of the cavity and vent hole impact the performance of the semiconductor package?

The size of the cavity and vent hole could affect the flow of under-fill material and the overall thermal management of the package. Further research is needed to determine the optimal dimensions for these features.

What materials are used for the under-fill layer and how do they impact the reliability of the semiconductor package?

The materials used for the under-fill layer play a crucial role in the reliability and performance of the semiconductor package. Understanding the properties of these materials and their interactions with other components is essential for optimizing the package design.

Original Abstract Submitted

disclosed are semiconductor packages and/or methods of fabricating the same. the semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. the package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. the first under-fill layer extends along the first vent hole to fill the cavity.